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Specman E
Interview Questions
TEST YOUR VERILOG SKILLS 1
(Q
i
1)
o
e
Identify
i
the
o
error
q
in
r
e
the
i
following
o
q
j
code.
b
[
7
:
0
]
i
=
o
e
{
2
{
5
}};
(Q
i
2)
o
e
i
When
o
are
q
instance
r
e
names
i
optional?
(Q
i
3)
o
e
In
i
the
o
following
q
program,
r
e
i
what
o
q
j
is
r
e
the
i
problem
o
and
q
how to
z
avoid
u
y
it
e
o
?
task
i
driver
;
input
i
read
;
www.testbench.in
input
i
[
7
:
0
]
o
e
write_d
;
begin
#
30
i
date_valid
o
e
=
i
1'b1
;
wait
(
read
i
==
o
e
1'b1
);
#
20
i
cpu_data
o
e
=
i
write_data
;
$display
(
"End
i
of
o
e
task"
);
end
endtask
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q
i
4)
o
e
How
i
many
o
levels
q
can
r
e
be
i
nested
o
q
j
using
r
e
`include
i
?
www.testbench.in
Ans:
You
i
can
o
e
nest
i
the
o
`include
q
compiler
r
e
directive
i
to
o
q
j
at
r
e
least
i
16
o
levels
.
(Q
i
5)
o
e
What
i
is
o
the
q
use
r
e
of
i
$countdrivers
o
q
j
?
Ans:
The
i
$countdrivers
o
e
system
i
function
o
is
q
provided
r
e
to
i
count
o
q
j
the
r
e
number
i
of
o
drivers
q
on a
z
specified
u
y
net
e
o
so
z
x
that bus contention can be identified.
(Q
i
6)
o
e
What
i
is
o
the
q
use
r
e
of
i
$getpattern
o
q
j
?
Ans:
The
i
system
o
e
function
i
$getpattern
o
provides
q
for
r
e
fast
i
processing
o
q
j
of
r
e
stimulus
i
patterns
o
that
q
have to
z
be
u
y
propagated
e
o
to
z
x
a large number of scalar inputs. The function reads stimulus patterns that have been loaded into a memory using the $readmemb or $readmemh system tasks.
www.testbench.in
reg
i
[
1
:
in_width
]
o
e
in_mem
[
1
:
patterns
];
integer
i
index
;
assign
i
{
i1
,
i2
,
i3
,
i4
,
i5
,
i6
,
i7
,
i8
,
i9
,
i10
}
o
e
=
i
$getpattern
(
in_mem
[
index
]);
(Q
i
7)
o
e
What
i
is
o
the
q
functionality
r
e
of
i
&&&
o
q
j
r
e
(not
i
&&
o
,
q
not &)
z
?
(Q
i
8)
o
e
How
i
to
o
get
q
copy
r
e
of
i
all
o
q
j
the
r
e
text
i
that
o
is
q
printed to
z
the
u
y
standard
e
o
output
z
x
in a log file ?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Ans:
i
Using
i
$log
(
"filename"
);
www.testbench.in
(Q
i
9)
o
e
What
i
is
o
the
q
use
r
e
of
i
PATHPULSE$
o
q
j
r
e
?
Ans:
PATHPULSE
$
i
specparam
o
e
is
i
used
o
to
q
control
r
e
pulse
i
handling
o
q
j
on
r
e
a
i
module
o
path
.
(Q
i
10)
o
e
i
in
o
statement
q
(
r
e
(a==b)
i
&&
o
q
j
(c
r
e
==
i
d)
o
)
q
, what
z
is
u
y
the
e
o
expression
z
x
coverage if always a=0,b=0,c=0,d=0 ?
(Q
i
11)
o
e
Difference
i
between
o
Reduction
q
and
r
e
Bitwise
i
operators?
Ans:
The
i
difference
o
e
is
i
that
o
bitwise
q
operations
r
e
are
i
on
o
q
j
bits
r
e
from
i
two
o
different
q
operands, whereas
z
reduction
u
y
operations
e
o
are
z
x
on the bits of the same operand. Reduction operators work bit by bit from right to left. Reduction operators perform a bitwise operation on a single vector operand and yield a 1-bit result Bitwise operators perform a bit-by-bit operation on two operands. They take each bit in one operand and perform the operation with the corresponding bit in the other operand.
www.testbench.in
(Q
i
12)
o
e
i
What
o
is
q
the
r
e
difference
i
between
o
q
j
the
r
e
following
i
two
o
lines
q
of Verilog
z
code?
#
5
i
a
o
e
=
i
b
;
a
i
=
o
e
#
5
i
b
;
Ans:
i
#
5
o
e
a
i
=
o
b
;
Wait
i
five
o
e
time
i
units
o
before
q
doing
r
e
the
i
action
o
q
j
for
r
e
"a
i
=
o
b;".
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
The
i
value
o
e
assigned
i
to
o
a
q
will
r
e
be
i
the
o
q
j
value
r
e
of
i
b
o
5
q
time units
z
hence.
a
i
=
o
e
#
5
i
b
;
The
i
value
o
e
of
i
b
o
is
q
calculated
r
e
and
i
stored
o
q
j
in
r
e
an
i
internal
o
temp
www.testbench.in
register.
i
After
o
e
five
i
time
o
units,
q
assign
r
e
this
i
stored
o
q
j
value
r
e
to
i
a.
(Q
i
13)
o
e
i
What
o
is
q
the
r
e
difference
i
between:
o
q
j
c
r
e
=
i
foo
o
?
q
a :
z
b;
u
y
and
e
o
if
z
x
(foo) c = a; else c = b;
Ans:
i
The
i
?
o
e
merges
i
answers
o
if
q
the
r
e
condition
i
is
o
q
j
"x",
r
e
so
i
for
o
instance
q
if foo
z
=
u
y
1'bx,
e
o
a
z
x
= 'b10, and b = 'b11, you'd get c = 'b1x.
On
i
the
o
e
other
i
hand,
o
if
q
treats
r
e
X's
i
or
o
q
j
Zs
r
e
as
i
FALSE,
o
so
q
you'd always
z
get
u
y
c
e
o
=
z
x
b.
(Q
i
14)
o
e
How
i
is
o
Verilog
q
implementation
r
e
independent
i
and
o
q
j
why
r
e
is
i
this
o
an
q
advantage?
www.testbench.in
(Q
i
15)
o
e
What
i
level
o
of
q
Verilog
r
e
is
i
used
o
q
j
in:
a
.
i
Test
o
e
benches
b
.
i
Synthesized
o
e
design
c
.
i
Net
o
e
list
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q
i
16)
o
e
i
what
o
is
q
the
r
e
difference
i
between
o
q
j
$fopen("filename");
r
e
and
i
$fopen("filename","w");
Ans:
If
i
type
o
e
is
i
omitted,
o
the
q
file
r
e
is
i
opened
o
q
j
for
r
e
writing,
i
and
o
a
q
multi channel
z
descriptor
u
y
mcd
e
o
is
z
x
returned. If type is supplied, the file is opened as specified by the value of type, and a file descriptor fd is returned. So in first statements , type is omitted and mcd is returned and in the second statement, fd is returned.
www.testbench.in
In
i
the
o
e
first
i
statement,
o
the
q
file
r
e
is
i
opened
o
q
j
for
r
e
read
i
and
o
write.
But
i
in
o
e
second
i
statement,
o
"w"
q
is
r
e
specified,
i
so
o
q
j
the
r
e
file
i
is
o
opened
q
for only
z
writing.
u
y
(Q
i
17)
o
e
i
What
o
is
q
the
r
e
difference
i
between
o
q
j
multi
r
e
channel
i
descriptors(mcd)
o
and
q
file descriptors(fd)?
Ans:
The
i
multi
o
e
channel
i
descriptor
o
mcd
q
is
r
e
a
i
32
o
q
j
bit
r
e
reg
i
in
o
which
q
a single
z
bit
u
y
is
e
o
set
z
x
indicating which file is opened. Unlike multi channel descriptors, file descriptors can not be combined via bitwise or in order to direct output to multiple files. Instead, files are opened via file descriptor for input, output, input and output, as well as for append operations, based on the value of type.
(Q
i
18)
o
e
i
How
o
to
q
generate
r
e
a
i
random
o
q
j
number?
www.testbench.in
(Q
i
19)
o
e
How
i
to
o
generate
q
a
r
e
random
i
number
o
q
j
which
r
e
is
i
less
o
the
q
100 ?
(Q
i
20)
o
e
How
i
to
o
generate
q
a
r
e
random
i
number
o
q
j
which
r
e
is
i
between
o
0
q
to 100
z
?
(Q
i
21)
o
e
i
What
o
is
q
the
r
e
advantage
i
of
o
q
j
Named
r
e
Port
i
Connection
o
over
q
Ordered Port
z
Connection
u
y
?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Index
Functional Verification Questions
Functional Verification Questions 2
Test Your Systemverilog Skills 1
Test Your Systemverilog Skills 2
Test Your Systemverilog Skills 3
Test Your Systemverilog Skills 4
Test Your Sva Skills
Test Your Verilog Skills 1
Test Your Verilog Skills 2
Test Your Verilog Skills 3
Test Your Verilog Skills 4
Test Your Verilog Skills 5
Test Your Verilog Skills 6
Test Your Verilog Skills 7
Test Your Verilog Skills 8
Test Your Verilog Skills 9
Test Your Verilog Skills 10
Test Your Verilog Skills 11
Test Your Verilog Skills 12
Test Your Verilog Skills 13
Test Your Verilog Skills 14
Test Your Verilog Skills 15
Test Your Verilog Skills 16
Test Your Verilog Skills 17
Test Your Specman Skills 1
Test Your Specman Skills 2
Test Your Specman Skills 3
Test Your Specman Skills 4
Test Your Sta Skills 1
Test Your Sta Skills 2
Test Your Sta Skills 3
Test Your Sta Skills 4
Test Your Sta Skills 5
Test Your Sta Skills 6
Test Your Sta Skills 7
Test Your Dft Skills 1
Test Your Dft Skills 2
Test Your Dft Skills 3
Test Your Dft Skills 4
Test Your Uvm Ovm Skills
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