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TEST YOUR VERILOG SKILLS 1



(Q i1)o eIdentifyi theoerror qinre the ifollowingoq jcode.
b
[7:0] i=o e{2{5}};

(Q i2)o ei Whenoare qinstancere names ioptional?

(Q i3)o eIni theofollowing qprogram,re iwhatoq jisre the iproblem oandqhow toz avoidu yite o?
task idriver;
input iread; www.testbench.in

input i[7:0]o ewrite_d;
begin
#30 idate_valido e=i 1'b1;
wait(read i==o e1'b1);
#20 icpu_datao e=i write_data;
$display("End iofo etask");
end
endtask
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(Q i4)o eHowi manyolevels qcanre be inestedoq jusingre `include i? www.testbench.in

Ans:
You
icano enesti theo`include qcompilerre directive itooq jatre least i16 olevels.

(Q i5)o eWhati isothe qusere of i$countdriversoq j?
Ans:


The i$countdriverso esystemi functionois qprovidedre to icountoq jthere number iof odriversqon az specifiedu ynete osozx that bus contention can be identified.



(Q i6)o eWhati isothe qusere of i$getpatternoq j?
Ans:


The isystemo efunctioni $getpatternoprovides qforre fast iprocessingoq jofre stimulus ipatterns othatqhave toz beu ypropagatede otozx a large number of scalar inputs. The function reads stimulus patterns that have been loaded into a memory using the $readmemb or $readmemh system tasks. www.testbench.in




reg i[1:in_width]o ein_mem[1:patterns];
integer iindex;
assign i{i1,i2,i3,i4,i5,i6,i7,i8,i9,i10}o e=i $getpattern(in_mem[index]);

(Q i7)o eWhati isothe qfunctionalityre of i&&&oq jre (not i&& o,qnot &)z ?

(Q i8)o eHowi tooget qcopyre of ialloq jthere text ithat oisqprinted toz theu ystandarde ooutputzx in a log file ? .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n

Ans: i
Using
i$log("filename"); www.testbench.in


(Q i9)o eWhati isothe qusere of iPATHPULSE$oq jre ?
Ans:
PATHPULSE$ ispecparamo eisi usedoto qcontrolre pulse ihandlingoq jonre a imodule opath.

(Q i10)o ei inostatement q(re (a==b) i&&oq j(cre == id) o)q, whatz isu ythee oexpressionzx coverage if always a=0,b=0,c=0,d=0 ?

(Q i11)o eDifferencei betweenoReduction qandre Bitwise ioperators?
Ans:


The idifferenceo eisi thatobitwise qoperationsre are ionoq jbitsre from itwo odifferentqoperands, whereasz reductionu yoperationse oarezx on the bits of the same operand. Reduction operators work bit by bit from right to left. Reduction operators perform a bitwise operation on a single vector operand and yield a 1-bit result Bitwise operators perform a bit-by-bit operation on two operands. They take each bit in one operand and perform the operation with the corresponding bit in the other operand. www.testbench.in




(Q i12)o ei Whatois qthere difference ibetweenoq jthere following itwo olinesqof Verilogz code?
#5 iao e=i b;
a
i=o e#5i b;
Ans:
i#5o eai =ob;


Wait ifiveo etimei unitsobefore qdoingre the iactionoq jforre "a i= ob;". .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n

The ivalueo eassignedi tooa qwillre be itheoq jvaluere of ib o5qtime unitsz hence.


a
i=o e#5i b;


The ivalueo eofi bois qcalculatedre and istoredoq jinre an iinternal otemp www.testbench.in

register. iAftero efivei timeounits, qassignre this istoredoq jvaluere to ia.



(Q i13)o ei Whatois qthere difference ibetween:oq jcre = ifoo o?qa :z b;u yande oifzx (foo) c = a; else c = b;

Ans: i


The i?o emergesi answersoif qthere condition iisoq j"x",re so ifor oinstanceqif fooz =u y1'bx,e oazx = 'b10, and b = 'b11, you'd get c = 'b1x.
On itheo eotheri hand,oif qtreatsre X's ioroq jZsre as iFALSE, osoqyou'd alwaysz getu yce o=zx b.



(Q i14)o eHowi isoVerilog qimplementationre independent iandoq jwhyre is ithis oanqadvantage?
www.testbench.in


(Q i15)o eWhati leveloof qVerilogre is iusedoq jin:
a
. iTesto ebenches
b
. iSynthesizedo edesign
c
. iNeto elist
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n


(Q i16)o ei whatois qthere difference ibetweenoq j$fopen("filename");re and i$fopen("filename","w");
Ans:


If itypeo eisi omitted,othe qfilere is iopenedoq jforre writing, iand oaqmulti channelz descriptoru ymcde oiszx returned. If type is supplied, the file is opened as specified by the value of type, and a file descriptor fd is returned. So in first statements , type is omitted and mcd is returned and in the second statement, fd is returned. www.testbench.in


In itheo efirsti statement,othe qfilere is iopenedoq jforre read iand owrite.
But iino esecondi statement,o"w" qisre specified, isooq jthere file iis oopenedqfor onlyz writing.u y



(Q i17)o ei Whatois qthere difference ibetweenoq jmultire channel idescriptors(mcd) oandqfile descriptors(fd)?
Ans:


The imultio echanneli descriptoromcd qisre a i32oq jbitre reg iin owhichqa singlez bitu yise osetzx indicating which file is opened. Unlike multi channel descriptors, file descriptors can not be combined via bitwise or in order to direct output to multiple files. Instead, files are opened via file descriptor for input, output, input and output, as well as for append operations, based on the value of type.



(Q i18)o ei Howoto qgeneratere a irandomoq jnumber?
www.testbench.in

(Q i19)o eHowi toogenerate qare random inumberoq jwhichre is iless otheq100 ?

(Q i20)o eHowi toogenerate qare random inumberoq jwhichre is ibetween o0qto 100z ?

(Q i21)o ei Whatois qthere advantage iofoq jNamedre Port iConnection ooverqOrdered Portz Connectionu y? .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n

Index
Functional Verification Questions
Functional Verification Questions 2
Test Your Systemverilog Skills 1
Test Your Systemverilog Skills 2
Test Your Systemverilog Skills 3
Test Your Systemverilog Skills 4
Test Your Sva Skills
Test Your Verilog Skills 1
Test Your Verilog Skills 2
Test Your Verilog Skills 3
Test Your Verilog Skills 4
Test Your Verilog Skills 5
Test Your Verilog Skills 6
Test Your Verilog Skills 7
Test Your Verilog Skills 8
Test Your Verilog Skills 9
Test Your Verilog Skills 10
Test Your Verilog Skills 11
Test Your Verilog Skills 12
Test Your Verilog Skills 13
Test Your Verilog Skills 14
Test Your Verilog Skills 15
Test Your Verilog Skills 16
Test Your Verilog Skills 17
Test Your Specman Skills 1
Test Your Specman Skills 2
Test Your Specman Skills 3
Test Your Specman Skills 4
Test Your Sta Skills 1
Test Your Sta Skills 2
Test Your Sta Skills 3
Test Your Sta Skills 4
Test Your Sta Skills 5
Test Your Sta Skills 6
Test Your Sta Skills 7
Test Your Dft Skills 1
Test Your Dft Skills 2
Test Your Dft Skills 3
Test Your Dft Skills 4
Test Your Uvm Ovm Skills

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