............COVERAGE DRIVEN CONSTRAINT RANDOM VERIFICATION ARCHITECTURE ..................... Verification Components Required For Cdcrv
..................... Stimulus
..................... Stimulus Generator
..................... Transactor
..................... Driver
..................... Monitor
..................... Assertion Based Monitor
..................... Data Checker
..................... Scoreboard
..................... Coverage
..................... Utilities
..................... Environment
..................... Tests
............PHASES OF VERIFICATION ..................... Verification Plan
..................... Building Testbench
..................... Writing Tests
..................... Integrating Code Coverage
..................... Analyze Coverage
............ONES COUNTER EXAMPLE ..................... Specification
..................... Test Plan
..................... Block Diagram
..................... Verification Environment Hierarchy
..................... Testbench Components
..................... Stimulus
..................... Driver
..................... Monitor
..................... Assertion Coverage
..................... Scoreboard
..................... Environment
..................... Top
..................... Tests
............VERIFICATION PLAN ..................... Verification Plan Contains The Following
..................... Overview
..................... Feature Extraction
..................... Resources, Budget And Schedule
..................... Verification Environment
..................... System Verilog Verification Flow
..................... Stimulus Generation Plan
..................... Checker Plan
..................... Coverage Plan
..................... Details Of Reusable Components