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Specman E
Interview Questions
TEST YOUR VERILOG SKILLS 17
(Q
i
283)
o
e
How
i
can
o
you
q
swap
r
e
2
i
integers
o
q
j
a
r
e
and
i
b,
o
without
q
using a
z
3rd
u
y
variable?
Ans:
There
i
are
o
e
many
i
solutions.
One
i
of
o
e
the
i
solution
o
is
q
bit
i
a,b;
a=a
i
XOR
o
e
b;
i
b=a
i
XOR
o
e
b;
i
www.testbench.in
a=
i
a
o
e
XOR
i
b;
o
(Q
i
284)
o
e
i
What
o
you
q
mean
r
e
by
i
inferring
o
q
j
latches?
r
e
(Q
i
285)
o
e
i
How
o
to
q
avoid
r
e
latches
i
in
o
q
j
your
r
e
design?
i
(Q
i
286)
o
e
i
What
o
is
q
sensitivity
r
e
list?
i
(Q
i
287)
o
e
i
If
o
you
q
miss
r
e
sensitivity
i
list
o
q
j
what
r
e
happens?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
www.testbench.in
(Q
i
288)
o
e
How
i
to
o
do
q
variable
r
e
part
i
select
o
q
j
of
r
e
a
i
vector???
(Q
i
289)
o
e
i
Find
o
the
q
bug
r
e
in
i
the
o
q
j
following
r
e
code
module
i
backdrive(input
o
e
wire
i
a);
o
q
wire
i
b;
assign
i
a
o
e
=
i
b;
o
q
endmodule
(Q
i
290)
o
e
How
i
to
o
use
q
generate
r
e
for
i
loop
o
q
j
to
r
e
instantiate
i
a
o
module?
q
www.testbench.in
(Q
i
291)
o
e
i
Difference
o
between
q
event
r
e
based
i
simulators
o
q
j
and
r
e
cycle
i
based
o
simulators.
(Q
i
292)
o
e
i
Explain
o
about
q
`resetall.
Ans:
When
i
`resetall
o
e
compiler
i
directive
o
is
q
encountered
r
e
during
i
compilation,
o
q
j
all
r
e
compiler
i
directives
o
are
q
set to
z
the
u
y
default
e
o
values.
This
i
is
o
e
useful
i
for
o
ensuring
q
that
r
e
only
i
those
o
q
j
directives
r
e
that
i
are
o
desired
q
in compiling
z
a
u
y
particular
e
o
source
z
x
file are active.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q
i
293)
o
e
i
How
o
do
q
you
r
e
implement
i
the
o
q
j
bi-directional
r
e
ports
i
in
o
Verilog
q
HDL?
www.testbench.in
module
i
bidirec
o
e
(oe,
i
clk,
o
inp,
q
outp,
r
e
bidir);
//
i
Port
o
e
Declaration
input
i
oe;
input
i
clk;
input
i
[7:0]
o
e
inp;
output
i
[7:0]
o
e
outp;
inout
i
[7:0]
o
e
bidir;
i
reg
i
[7:0]
o
e
a;
reg
i
[7:0]
o
e
b;
www.testbench.in
assign
i
bidir
o
e
=
i
oe
o
?
q
a
r
e
:
i
8'bZ
o
q
j
;
assign
i
outp
o
e
=
i
b;
//
i
Always
o
e
Construct
always
i
@
o
e
(posedge
i
clk)
begin
b
i
<=
o
e
bidir;
a
i
<=
o
e
inp;
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
end
endmodule
i
www.testbench.in
(Q
i
294)
o
e
i
If
o
the
q
part-select
r
e
is
i
out
o
q
j
of
r
e
the
i
address
o
bounds
q
or the
z
part-select
u
y
is
e
o
x
z
x
or z, then the value is returned by the reference ?
Ans:
Its
i
o
e
'bx
i
.
(Q
i
295)
o
e
What
i
is
o
the
q
difference
r
e
between
i
constant
o
q
j
function
r
e
and
i
ordinary
o
function
q
?
Ans:
Constant
i
function
o
e
calls
i
are
o
used
q
to
r
e
support
i
the
o
q
j
building
r
e
of
i
complex
o
calculations
q
of values
z
at
u
y
elaboration
e
o
time
z
x
. A constant function call shall be a function invocation of a constant function local to the calling module where the arguments to the function are constant expressions. Constant functions are a subset of normal Verilog functions that shall meet the following constraints:
--
i
They
o
e
shall
i
contain
o
no
q
hierarchical
r
e
references.
www.testbench.in
--
i
Any
o
e
function
i
invoked
o
within
q
a
r
e
constant
i
function
o
q
j
shall
r
e
be
i
a
o
constant
q
function local
z
to
u
y
the
e
o
current
z
x
module. System functions shall not be invoked.
--
i
All
o
e
system
i
tasks
o
within
q
a
r
e
constant
i
function
o
q
j
shall
r
e
be
i
ignored.
--
i
All
o
e
system
i
functions
o
within
q
a
r
e
constant
i
function
o
q
j
shall
r
e
be
i
illegal.
--
i
The
o
e
only
i
system
o
task
q
that
r
e
may
i
be
o
q
j
invoked
r
e
is
i
$display,
o
and
q
it shall
z
be
u
y
ignored
e
o
when
z
x
invoked at elaboration time.
(Q
i
296)
o
e
What
i
is
o
genvar
q
?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Ans:
An
i
index
o
e
variable
i
that
o
shall
q
only
r
e
be
i
declared
o
q
j
for
r
e
use
i
in
o
generate
q
statements shall
z
be
u
y
declared
e
o
as
z
x
a genvar.
(Q
i
297)
o
e
In
i
the
o
case
q
of
r
e
multiple
i
defparams
o
q
j
for
r
e
a
i
single
o
parameter,
q
what value
z
it
u
y
will
e
o
take?
www.testbench.in
Ans:
The
i
parameter
o
e
takes
i
the
o
value
q
of
r
e
the
i
last
o
q
j
defparam
r
e
statement
i
encountered
o
in
q
the source
z
text.
u
y
When
e
o
defparams
z
x
are encountered in multiple source files, e.g., found by library searching, the defparam from which the parameter takes it s value is undefined.
(Q
i
298)
o
e
How
i
to
o
model
q
a
r
e
queue
i
of
o
q
j
integers?
Ans:
The
i
set
o
e
of
i
tasks
o
and
q
functions
r
e
that
i
create
o
q
j
and
r
e
manage
i
queues
o
follow:
$q_initialize
i
(q_id,
o
e
q_type,
i
max_length,
o
status)
q
;
$q_add
i
(q_id,
o
e
job_id,
i
inform_id,
o
status)
q
;
$q_remove
i
(q_id,
o
e
job_id,
i
inform_id,
o
status)
q
;
$q_full
i
(q_id,
o
e
status)
i
;
www.testbench.in
$q_exam
i
(q_id,
o
e
q_stat_code,
i
q_stat_value,
o
status)
q
;
Index
Functional Verification Questions
Functional Verification Questions 2
Test Your Systemverilog Skills 1
Test Your Systemverilog Skills 2
Test Your Systemverilog Skills 3
Test Your Systemverilog Skills 4
Test Your Sva Skills
Test Your Verilog Skills 1
Test Your Verilog Skills 2
Test Your Verilog Skills 3
Test Your Verilog Skills 4
Test Your Verilog Skills 5
Test Your Verilog Skills 6
Test Your Verilog Skills 7
Test Your Verilog Skills 8
Test Your Verilog Skills 9
Test Your Verilog Skills 10
Test Your Verilog Skills 11
Test Your Verilog Skills 12
Test Your Verilog Skills 13
Test Your Verilog Skills 14
Test Your Verilog Skills 15
Test Your Verilog Skills 16
Test Your Verilog Skills 17
Test Your Specman Skills 1
Test Your Specman Skills 2
Test Your Specman Skills 3
Test Your Specman Skills 4
Test Your Sta Skills 1
Test Your Sta Skills 2
Test Your Sta Skills 3
Test Your Sta Skills 4
Test Your Sta Skills 5
Test Your Sta Skills 6
Test Your Sta Skills 7
Test Your Dft Skills 1
Test Your Dft Skills 2
Test Your Dft Skills 3
Test Your Dft Skills 4
Test Your Uvm Ovm Skills
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