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TEST YOUR VERILOG SKILLS 17


(Q i283)o eHowi canoyou qswapre 2 iintegersoq jare and ib, owithoutqusing az 3rdu yvariable?
Ans:


There iareo emanyi solutions.
One iofo ethei solutionois q



bit ia,b;

a=a iXORo eb;i
b=a iXORo eb;i www.testbench.in

a= iao eXORi b;o

(Q i284)o ei Whatoyou qmeanre by iinferringoq jlatches?re

(Q i285)o ei Howoto qavoidre latches iinoq jyourre design? i

(Q i286)o ei Whatois qsensitivityre list? i

(Q i287)o ei Ifoyou qmissre sensitivity ilistoq jwhatre happens? .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n

www.testbench.in

(Q i288)o eHowi toodo qvariablere part iselectoq jofre a ivector???

(Q i289)o ei Findothe qbugre in itheoq jfollowingre code

module ibackdrive(inputo ewirei a);o q
wire ib;
assign iao e=i b;o q
endmodule

(Q i290)o eHowi toouse qgeneratere for iloopoq jtore instantiate ia omodule?q www.testbench.in


(Q i291)o ei Differenceobetween qeventre based isimulatorsoq jandre cycle ibased osimulators.

(Q i292)o ei Explainoabout q`resetall.
Ans:


When i`resetallo ecompileri directiveois qencounteredre during icompilation,oq jallre compiler idirectives oareqset toz theu ydefaulte ovalues.
This iiso eusefuli foroensuring qthatre only ithoseoq jdirectivesre that iare odesiredqin compilingz au yparticulare osourcezx file are active.


.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n

(Q i293)o ei Howodo qyoure implement itheoq jbi-directionalre ports iin oVerilogqHDL?
www.testbench.in

module ibidireco e(oe,i clk,oinp, qoutp,re bidir);

// iPorto eDeclaration
input ioe;
input iclk;
input i[7:0]o einp;
output i[7:0]o eoutp;
inout i[7:0]o ebidir;i
reg i[7:0]o ea;
reg i[7:0]o eb; www.testbench.in

assign ibidiro e=i oeo? qare : i8'bZoq j;
assign ioutpo e=i b;
// iAlwayso eConstruct
always i@o e(posedgei clk)
begin
b i<=o ebidir;
a i<=o einp; .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n

end
endmodule i
www.testbench.in

(Q i294)o ei Ifothe qpart-selectre is ioutoq jofre the iaddress oboundsqor thez part-selectu yise oxzx or z, then the value is returned by the reference ?
Ans:
Its io e'bxi .


(Q i295)o eWhati isothe qdifferencere between iconstantoq jfunctionre and iordinary ofunctionq?

Ans:


Constant ifunctiono ecallsi areoused qtore support itheoq jbuildingre of icomplex ocalculationsqof valuesz atu yelaboratione otimezx . A constant function call shall be a function invocation of a constant function local to the calling module where the arguments to the function are constant expressions. Constant functions are a subset of normal Verilog functions that shall meet the following constraints:
-- iTheyo eshalli containono qhierarchicalre references. www.testbench.in

-- iAnyo efunctioni invokedowithin qare constant ifunctionoq jshallre be ia oconstantqfunction localz tou ythee ocurrentzx module. System functions shall not be invoked.
-- iAllo esystemi tasksowithin qare constant ifunctionoq jshallre be iignored.
-- iAllo esystemi functionsowithin qare constant ifunctionoq jshallre be iillegal.
-- iTheo eonlyi systemotask qthatre may ibeoq jinvokedre is i$display, oandqit shallz beu yignorede owhenzx invoked at elaboration time.



(Q i296)o eWhati isogenvar q? .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n

Ans:


An iindexo evariablei thatoshall qonlyre be ideclaredoq jforre use iin ogenerateqstatements shallz beu ydeclarede oaszx a genvar.



(Q i297)o eIni theocase qofre multiple idefparamsoq jforre a isingle oparameter,qwhat valuez itu ywille otake? www.testbench.in

Ans:


The iparametero etakesi theovalue qofre the ilastoq jdefparamre statement iencountered oinqthe sourcez text.u yWhene odefparamszx are encountered in multiple source files, e.g., found by library searching, the defparam from which the parameter takes it s value is undefined.



(Q i298)o eHowi toomodel qare queue iofoq jintegers?
Ans:


The iseto eofi tasksoand qfunctionsre that icreateoq jandre manage iqueues ofollow:
$q_initialize i(q_id,o eq_type,i max_length,ostatus) q;
$q_add i(q_id,o ejob_id,i inform_id,ostatus) q;
$q_remove i(q_id,o ejob_id,i inform_id,ostatus) q;
$q_full i(q_id,o estatus)i ; www.testbench.in

$q_exam i(q_id,o eq_stat_code,i q_stat_value,ostatus) q;


Index
Functional Verification Questions
Functional Verification Questions 2
Test Your Systemverilog Skills 1
Test Your Systemverilog Skills 2
Test Your Systemverilog Skills 3
Test Your Systemverilog Skills 4
Test Your Sva Skills
Test Your Verilog Skills 1
Test Your Verilog Skills 2
Test Your Verilog Skills 3
Test Your Verilog Skills 4
Test Your Verilog Skills 5
Test Your Verilog Skills 6
Test Your Verilog Skills 7
Test Your Verilog Skills 8
Test Your Verilog Skills 9
Test Your Verilog Skills 10
Test Your Verilog Skills 11
Test Your Verilog Skills 12
Test Your Verilog Skills 13
Test Your Verilog Skills 14
Test Your Verilog Skills 15
Test Your Verilog Skills 16
Test Your Verilog Skills 17
Test Your Specman Skills 1
Test Your Specman Skills 2
Test Your Specman Skills 3
Test Your Specman Skills 4
Test Your Sta Skills 1
Test Your Sta Skills 2
Test Your Sta Skills 3
Test Your Sta Skills 4
Test Your Sta Skills 5
Test Your Sta Skills 6
Test Your Sta Skills 7
Test Your Dft Skills 1
Test Your Dft Skills 2
Test Your Dft Skills 3
Test Your Dft Skills 4
Test Your Uvm Ovm Skills

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