He is working with Synopsys as R&D Engineer. He has more than 3 years of experience as ASIC Design Verification Engineer. Prior to synopsys, he was working with Axiom Design Automation and Ample Communication. He is expertise in various Hardware verification languages and methodologies. He has experience in Verification of Ethernet,PCI Express and Interlaken.
He is an M.Tech in VLSI Design From Sathyabama University, Chennai.

You can reach him at: gopi@testbench.in
Connect to Gopi @ Linkedin : http://in.linkedin.com/in/systemverilog

Naresh Maddipati

You can reach him at: naresh@testbench.in

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