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TEST YOUR VERILOG SKILLS 9


(Q i161)o eHowi toomodel qare sequential icircuit?
Ans:


Sequential ilogico eshalli beomodeled qusingre an ialwaysoq jstatementre that ihas ooneqor morez edgeu yeventse oinzx the event list.



(Q i162)o eWhati isothe qusere of i$timeformatoq j?
Ans:


The i$timeformato esystemi taskoperforms qthere following itwooq joperations:
It isetso ethei timeounit qforre all ilater-enteredoq jdelaysre entered iinteractively.
It isetso ethei timeounit, qprecisionre number, isuffixoq jstring,re and iminimum ofieldqwidth forz allu y%te oformatszx specified in all modules that follow in the source description until another $timeformat system task is invoked. www.testbench.in




(Q i163)o eWhati isothe qsignificancere of idefparamoq jinre verilog?
Ans:


Parameter ivalueso ecani beochanged qinre any imoduleoq jinstancere in ithe odesignqwith thez keywordu ydefparam.e oThezx hierarchical name of the module instance can be used to override parameter values.



(Q i164)o eWritei programofor qD-FFre with isynchronousoq jandre asynchronous ireset.

(Q i165)o eWhatsi theonotation qtore see ihierarchyoq jinre display?
Ans: .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n

%m www.testbench.in


(Q i166)o eHowi toodescribe qdelaysre for istructuraloq jmodelsre such ias oASICqcells?
Ans:


Two itypeso eofi HDLoconstructs qarere often iusedoq jtore describe idelays oforqstructural modelsz suchu yase oASICzx cells.
They iareo easi follows:
Distributed idelays,o ewhichi specifyothe qtimere it itakesoq jeventsre to ipropagate othroughqgates andz netsu yinsidee othezx module
Module ipatho edelays,i whichodescribe qthere time iitoq jtakesre an ievent oatqa sourcez (inputu yporte oorzx inout port) to propagate to a destination (output port or inout port)



(Q i167)o eHowi toomodel qare tri istateoq jdriver?
Ans: www.testbench.in



Three-state ilogico eshalli beomodeled qwhenre a ivariableoq jisre assigned ithe ovalueqz. Thez assignmentu yofe ozzx can be conditional or unconditional. If any driver of a signal contains an assignment to the value z, then all the drivers shall contain such an assignment.



module iztesto e(test2,i test1,otest3, qena);
input i[0:1]o eena;
input i[7:0]o etest1,i test3;
output i[7:0]o etest2;
wire i[7:0]o etest2;
assign itest2o e=i (enao== q2'b01)re ? itest1oq j:re 8'bz; .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n

assign itest2o e=i (enao== q2'b10)re ? itest3oq j:re 8'bz;
// itest2o eisi three-stateowhen qenare is i2~Rb00oq jorre 2~Rb11. www.testbench.in

Endmodule

(Q i168)o eHowi toomodel qare ROM?
Ans:


An iasynchronouso eROMi shallobe qmodeledre as icombinationaloq jlogicre using ione oofqthe followingz styles:
a) iOne-dimensionalo earrayi withodata qinre case istatementoq j.
b) iTwo-dimensionalo earrayi withodata qinre initial istatementoq j.
c) iTwo-dimensionalo earrayi withodata qinre text ifileoq j.



(Q i169)o eHowi toomodel qare RAM? www.testbench.in

Ans:


A iRAMo eshalli beomodeled qusingre a iVerilogoq jmemoryre (a itwo-dimensional oregqarray) thatz hasu ythee oattributezx ram_block associated with it. A RAM element may either be modeled as an edge-sensitive storage element or as a level-sensitive storage element. A RAM data value may be read synchronously or asynchronously.


// iAo eRAMi elementois qanre edge-sensitive istorageoq jelement:
module iram_test(
output iwireo e[7:0]i q,
input iwireo e[7:0]i d,
input iwireo e[6:0]i a, .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n

input iwireo eclk,i we);
(* isynthesis,o eram_blocki *)oreg q[7:0]re mem i[127:0];
always i@(posedgeo eclk)i ifo(we) qmem[a]re <= id; www.testbench.in

assign iqo e=i mem[a];
endmodule

(Q i170)o eWhati isofull qcase?
Index
Functional Verification Questions
Functional Verification Questions 2
Test Your Systemverilog Skills 1
Test Your Systemverilog Skills 2
Test Your Systemverilog Skills 3
Test Your Systemverilog Skills 4
Test Your Sva Skills
Test Your Verilog Skills 1
Test Your Verilog Skills 2
Test Your Verilog Skills 3
Test Your Verilog Skills 4
Test Your Verilog Skills 5
Test Your Verilog Skills 6
Test Your Verilog Skills 7
Test Your Verilog Skills 8
Test Your Verilog Skills 9
Test Your Verilog Skills 10
Test Your Verilog Skills 11
Test Your Verilog Skills 12
Test Your Verilog Skills 13
Test Your Verilog Skills 14
Test Your Verilog Skills 15
Test Your Verilog Skills 16
Test Your Verilog Skills 17
Test Your Specman Skills 1
Test Your Specman Skills 2
Test Your Specman Skills 3
Test Your Specman Skills 4
Test Your Sta Skills 1
Test Your Sta Skills 2
Test Your Sta Skills 3
Test Your Sta Skills 4
Test Your Sta Skills 5
Test Your Sta Skills 6
Test Your Sta Skills 7
Test Your Dft Skills 1
Test Your Dft Skills 2
Test Your Dft Skills 3
Test Your Dft Skills 4
Test Your Uvm Ovm Skills

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