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Constructs
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Specman E
Interview Questions
TEST YOUR SYSTEMVERILOG SKILLS 1
(Q
i
1)
o
e
When
i
import
o
is
q
used
r
e
and
i
when
o
q
j
`include
r
e
is
i
used?
o
(Q
i
2)
o
e
What
i
is
o
the
q
output
r
e
of
i
the
o
q
j
below
r
e
code
i
?
o
i
class
o
e
mycls
i
#(
type
o
T
q
=
int
r
e
)
i
;
i
static
o
e
int
i
a
o
=
q
static_function
()
r
e
;
i
static
o
e
function
i
int
o
static_func
();
i
$display
(
"In
o
e
class
i
mycls#()"
);
i
return
o
e
10
i
;
www.testbench.in
i
endfunction
o
e
:
i
static_function
i
endclass
o
e
:
i
mycls
i
module
o
e
mod_def
();
i
initial
i
begin
i
end
i
endmodule
:
mod_def
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
www.testbench.in
i
If
o
e
the
i
below
o
line
q
is
r
e
added
i
to
o
q
j
above
r
e
code
,
i
then
o
what
q
will be
z
the
u
y
output
e
o
?
i
typedef
o
e
cls_def
#(
int
)
i
cl_int
;
(Q
i
3)
o
e
In
i
the
o
below
q
example,
r
e
"a1
i
=
o
q
j
b1"
r
e
is
i
not
o
allowed.
q
Why
z
is
u
y
it
e
o
not
z
x
allowed and what is the solution ?
class
i
a
o
e
#(
type
i
T
=
int
);
i
o
e
virtual
i
function
o
void
q
func1
();
www.testbench.in
i
o
e
i
o
$display
(
"Inside
q
base"
);
i
o
e
endfunction
i
:
o
func1
endclass
class
i
b
o
e
extends
i
a
o
#(
real
);
i
o
e
virtual
i
function
o
void
q
func1
();
i
o
e
i
o
$display
(
"Inside
q
derived"
);
i
o
e
endfunction
i
:
o
func1
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
endclass
www.testbench.in
module
i
top
;
a
i
a1
;
b
i
b1
=
new
();
initial
i
begin
i
a1
o
e
=
i
b1
;
i
a1
.
func1
();
end
www.testbench.in
endmodule
i
:
o
e
top
(Q
i
4)
o
e
What
i
is
o
the
q
name
r
e
of
i
the
o
q
j
method
r
e
in
i
which
o
covergroup
q
is constructed
z
in
u
y
your
e
o
project
z
x
?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q
i
5)
o
e
A
i
method
o
is
q
defined
r
e
a
i
virtual.
o
q
j
Using
r
e
extended
i
class
o
handle/object,
q
how to
z
call
u
y
the
e
o
virtual
z
x
method defined in base class?
(Q
i
6)
o
e
What
i
is
o
the
q
difference
r
e
B/W
i
the
o
q
j
variable
r
e
in
i
model
o
and
q
static variable
z
in
u
y
class
e
o
?
www.testbench.in
(Q
i
7)
o
e
What
i
is
o
the
q
difference
r
e
B/W
i
static,
o
q
j
automatic
r
e
and
i
dynamic
o
variables
q
?
(Q
i
8)
o
e
What
i
is
o
the
q
difference
r
e
B/W
i
verilog
o
q
j
function
r
e
and
i
SV
o
function
q
?
(Q
i
9)
o
e
What
i
is
o
the
q
output
r
e
of
i
the
o
q
j
following
r
e
program
i
?
program
i
main
();
i
o
e
i
initial
o
begin
www.testbench.in
i
o
e
i
o
q
r
e
i
fork
i
o
e
i
o
q
r
e
i
o
q
j
r
e
i
o
q
#
25
$display
(
"time
z
=
u
y
0
e
o
#
z
x
T25 "
,
$time
);
i
o
e
i
o
q
r
e
i
join_none
i
o
e
i
o
q
r
e
i
fork
i
o
e
i
o
q
r
e
i
o
q
j
r
e
i
o
q
z
#
20
u
y
e
o
$display
(
"
z
x
time = 0 # T20 "
,
$time
);
i
o
e
i
o
q
r
e
i
o
q
j
r
e
i
o
q
z
#
10
u
y
e
o
$display
(
"
z
x
time = 0 # T10 "
,
$time
);
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
i
o
e
i
o
q
r
e
i
o
q
j
r
e
i
o
q
z
#
5
u
y
e
o
z
x
$display
(
" time = 0 # T5 "
,
$time
);
i
o
e
i
o
q
r
e
i
o
q
j
r
e
join_any
i
o
e
i
o
q
r
e
i
o
q
j
disable
r
e
fork
;
i
o
e
i
o
end
www.testbench.in
i
o
e
i
initial
i
o
e
i
#
100
o
$finish
;
endprogram
(Q
i
10)
o
e
Why
i
Constructor
o
is
q
not
r
e
virtual
i
?
(Q
i
11)
o
e
Do
i
we
o
need
q
"virtual
r
e
constructor"
i
functionality
o
q
j
?
r
e
If
i
yes,
o
then
q
why is
z
it
u
y
required
e
o
?
www.testbench.in
(Q
i
12)
o
e
How
i
to
o
achieve
q
"virtual
r
e
constructor"
i
functionality
o
q
j
?
(Q
i
13)
o
e
Lets
i
say
o
I
q
have
r
e
transactions
i
a,b,c,d,e.
i
o
e
i
o
q
r
e
i
I
o
q
j
would
r
e
like
i
to
o
generate
q
transaction series
z
like
i
o
e
i
o
q
r
e
i
(1)A,
o
q
j
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
i
o
e
i
o
q
r
e
i
(2)
o
q
j
B
r
e
or
i
C,
i
o
e
i
o
q
r
e
i
(3)D,
i
o
e
i
o
q
r
e
i
(4)
o
q
j
if
r
e
B
i
is
o
generated
q
in second
z
position
u
y
then
e
o
generate
z
x
D and next go to (5) or jump to (1) again,
i
o
e
i
o
q
r
e
i
(5)
o
q
j
E,
r
e
go
i
back
o
to
q
(1)
www.testbench.in
i
o
e
i
o
q
How
r
e
to
i
implement
o
q
j
this
r
e
?
(Q
i
14)
o
e
Write
i
a
o
$display
q
stamen
r
e
to
i
print
o
q
j
the
r
e
value
i
in
o
a
q
enumerated variable.
z
(Q
i
15)
o
e
What
i
is
o
the
q
different
r
e
between
i
`define
o
q
j
and
r
e
"let"
i
?
(Q
i
16)
o
e
Why
i
default
o
clocking
q
block
r
e
is
i
required
o
q
j
?
(Q
i
17)
o
e
What
i
is
o
the
q
output
r
e
of
i
the
o
q
j
following
r
e
?
www.testbench.in
module
i
ques
();
i
o
e
i
o
string
q
strin
[
7
]
r
e
;
i
o
e
i
o
int
q
i
,
j
,
k
,
file
;
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
i
o
e
i
o
initial
q
begin
i
o
e
i
o
q
r
e
i
o
q
j
string
r
e
s
;
i
o
e
i
o
q
r
e
i
o
q
j
file
r
e
=
$fopen
(
"file.txt"
,
"r"
);
i
o
e
i
o
q
r
e
i
o
q
j
while
r
e
(!
$feof
(
file
))
begin
i
o
e
i
o
q
r
e
i
o
q
j
r
e
i
o
q
k
=
$fscanf
(
file
,
""
,
s
);
www.testbench.in
i
o
e
i
o
q
r
e
i
o
q
j
r
e
i
o
q
strin
[
i
]
=
s
;
i
o
e
i
o
q
r
e
i
o
q
j
r
e
i
o
q
i
++;
i
o
e
i
o
q
r
e
i
o
q
j
end
i
o
e
i
o
q
r
e
i
o
q
j
$fclose
(
file
);
i
o
e
i
o
foreach
(
strin
[
j
])
i
o
e
i
o
q
r
e
i
o
q
j
$display
(
"index
r
e
j=
i
0
o
q
string ="
,
j
,
strin
[
j
]);
i
o
e
i
o
$finish
;
i
o
e
i
o
end
endmodule
www.testbench.in
content
i
in
o
e
file
.
txt
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
================
aa
bb
cc
================
Ans:
www.testbench.in
Index
i
j=0
o
e
i
string
o
=
q
aa
Index
i
j=1
o
e
i
string
o
=
q
bb
Index
i
j=2
o
e
i
string
o
=
q
cc
Index
i
j=3
o
e
i
string
o
=
q
cc
The
i
data
o
e
"cc"
i
is
o
read
q
twice.
r
e
This
i
is
o
e
because
i
of
o
$feof.
q
(Q
i
18)
o
e
How
i
to
o
deallocate
q
an
r
e
object
i
?
Ans:
When
i
an
o
e
object
i
is
o
no
q
longer
r
e
needed,
i
SystemVerilog
o
q
j
automatically
r
e
reclaims
i
the
o
memory,
q
making it
z
available
u
y
for
e
o
reuse.
z
x
The automatic memory management system is an integral part of SystemVerilog.
www.testbench.in
If
i
user
o
e
want
i
to
o
deallocate,
q
he
r
e
can
i
just
o
q
j
assign
r
e
null
i
to
o
the
q
object.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
i
style="background-color:
o
e
#9cffff">
EXAMPLE:
testclass
i
b
;
o
e
//
i
o
Declare
q
a
r
e
handle
i
b
o
q
j
for
r
e
testclass
b
i
=
o
e
new
;
i
o
q
r
e
//
i
Construct
o
q
j
r
e
a
i
testclass
o
object
q
and stores
z
the
u
y
address
e
o
in
z
x
b ."new" allocate space for testclass
b
=
null
;
i
o
e
i
o
q
//Deallocate
r
e
the
i
object.Means
o
q
j
Deallocate
r
e
the
i
memory
o
space
q
for object.
(Q
i
19)
o
e
What
i
is
o
callback
q
?
Ans:
www.testbench.in
Testbenches
i
o
e
must
i
provide
o
a
q
"hook"
r
e
where
i
the
o
q
j
test
r
e
program
i
can
o
inject
q
new code
z
without
u
y
modifying
e
o
the
z
x
original classes.
Take
i
an
o
e
example:
i
Suppose
o
u
q
want
r
e
to
i
inject
o
q
j
a
r
e
new
i
functionality
o
q
in the
z
driver
u
y
without
e
o
modifying
z
x
the code. You can add the new functionality in pre_callback task or post-callback task,without modifying Driver task.
task
i
Driver
::
run
;
forever
i
begin
...
<
pre_callback
>
i
o
e
//It
i
calls
o
the
q
function
r
e
pre_callback.
transmit
(
tr
);
end
endtask
www.testbench.in
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
task
i
pre_callback
;
endtask
For
i
more
o
e
information,
i
Click on the below link
http://www.testbench.in/VM_08_VMM_CALLBACK.html
(Q
i
20)
o
e
What
i
is
o
factory
q
pattern
r
e
?
Ans:
i
style="background-color:
o
e
#9cffff">
EXAMPLE::
www.testbench.in
class
i
Generator
;
Transaction
i
tr
;
mailbox
i
mbx
;
tr
i
=
o
e
new
;
task
i
run
;
i
o
e
repeat
i
(
10
)
i
o
e
i
o
begin
i
o
e
i
o
assert
(
tr
.
randomize
);
i
o
e
i
o
mbx
.
put
(
tr
);
q
//
r
e
Send
i
out
o
q
j
transaction
i
o
e
i
o
end
www.testbench.in
endtask
endclass
Bug::Here
i
Object
o
e
"tr"
i
is
o
constructed
q
once
r
e
outside
i
the
o
q
j
loop.
r
e
Then
i
"tr"
o
is
q
randomized and
z
put
u
y
them
e
o
into
z
x
mailbox "mbx".But mailbox "mbx" holds only handles,not objects.Therefore Mailbox contains multiple handles pointing to single object.Here code gets the last set of random values.
Solution::Loop
i
should
o
e
contain
i
1)Constructing
i
object
o
e
i
o
q
r
e
i
o
q
j
r
e
i
o
q
z
u
y
e
o
z
x
2)Randomizing
i
object
o
e
i
3)Puttting
i
into
o
e
mailbox
task
i
run
;
i
o
e
repeat
i
(
10
)
www.testbench.in
i
o
e
i
o
begin
i
o
e
i
o
tr
q
=
new
();
r
e
i
o
q
j
r
e
i
o
q
z
u
y
e
o
//1.Constructing
i
o
e
i
o
assert
(
tr
.
randomize
);
//2.Randomize
i
o
e
i
o
mbx
.
put
(
tr
);
q
r
e
i
o
q
j
r
e
i
o
q
//3.Putting
z
into
u
y
mailbox
i
o
e
i
o
end
endtask
Second
i
Bug:
o
e
The
i
run
o
task
q
constructs
r
e
a
i
o
q
j
transaction
r
e
and
i
immediately
o
randomizes
q
it. Means
z
transaction
u
y
"tr"
e
o
uses
z
x
whatever constraints are turned on by default.
Solution
i
:
o
e
Separate
i
the
o
construction
q
of
r
e
tr
i
from
o
q
j
its
r
e
randomization
i
by
o
using
q
a method
z
called
u
y
e
o
"Factory
z
x
Pattern".
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Factory
i
Pattern:
o
e
i
www.testbench.in
1)construct
i
a
o
e
blueprint
i
object
o
2)Randomize
i
this
o
e
blueprint(
i
It
o
has
q
correct
r
e
random
i
values
o
q
j
)
3)Make
i
a
o
e
copy
i
of
o
this
q
object
r
e
4)Put
i
into
o
e
mailbox
class
i
Generator
;
mailbox
i
mbx
;
Transaction
i
blueprint
;
i
o
e
blueprint
i
=
o
new
;
//1.Constructing
q
Blue
r
e
print
task
i
run
;
www.testbench.in
Transaction
i
tr
;
Repeat
(
10
}
i
o
e
begin
i
o
e
assert
(
blueprint
.
randomize
);
i
//2.Randomizing
o
Blue
q
print
i
o
e
tr
i
=
o
blueprint
.
copy
;
q
//
r
e
i
3.Copy
o
q
j
the
r
e
blueprint
i
o
e
mbx
.
put
(
tr
);
i
//
o
4.Put
q
into
r
e
mailbox
i
o
e
end
endtask
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
endclass
www.testbench.in
(Q
i
21)
o
e
Explain
i
the
o
difference
q
between
r
e
data
i
types
o
q
j
logic
r
e
and
i
reg
o
and
q
wire .
Ans:
WIRE:
1.
i
Wire
o
e
is
i
just
o
an
q
interconnection
r
e
between
i
two
o
q
j
elements
r
e
which
i
does
o
not
q
have any
z
driving
u
y
strength
2.
i
It
o
e
is
i
used
o
for
q
modeling
r
e
combinational
i
circuit
o
q
j
as
r
e
it
i
cannot
o
store
q
a value.
3.
i
Wire
o
e
has
i
a
o
default
q
value
r
e
of
i
"z"
o
q
j
and
r
e
get
i
values
o
continuously
q
from the
z
outputs
u
y
of
e
o
devices
z
x
to which they are connected to.
4.Example:
i
o
e
i
o
q
r
e
wire
i
A
;
i
o
e
i
o
q
r
e
assign
i
A
o
q
j
=
r
e
b
&
c
;
www.testbench.in
Note:wire
i
A
o
e
is
i
evaluated
o
for
q
every
r
e
simulation
i
delta
o
q
j
time.
r
e
So
i
there
o
is
q
no need
z
to
u
y
store
e
o
the
z
x
value.
REG
1.
i
Reg
o
e
is
i
a
o
4
q
state
r
e
unsigned
i
variable
o
q
j
that
r
e
can
i
hold
o
a
q
value and
z
retains
u
y
until
e
o
a
z
x
new value is assigned to it.
2.
i
Register
o
e
data
i
type
o
can
q
be
r
e
used
i
for
o
q
j
modeling
r
e
both
i
combinational
o
and
q
sequential logic
3.
i
Default
o
e
value
i
for
o
register
q
is
r
e
"x"
i
and
o
q
j
it
r
e
doesn't
i
require
o
any
q
driver to
z
assign
u
y
value
e
o
like
z
x
wire. It can be driven from initial and always block. Values of the register can be changed anytime in the simulation by assigning a new value to register.
4.Example:
i
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
i
o
e
i
o
q
r
e
i
o
q
j
r
e
i
o
q
reg
A
;
i
o
e
i
o
q
r
e
i
o
q
j
r
e
i
o
q
always
@
z
(
b
u
y
or
e
o
c
)
i
o
e
i
o
q
r
e
i
o
q
j
r
e
i
o
q
begin
www.testbench.in
i
o
e
i
o
q
r
e
i
o
q
j
r
e
i
o
q
A
=
b
&
c
;
i
o
e
i
o
q
r
e
i
o
q
j
r
e
i
o
q
end
Note:A
i
is
o
e
declared
i
as
o
reg
q
which
r
e
can
i
be
o
q
j
evaluated
r
e
only
i
when
o
there
q
is a
z
change
u
y
in
e
o
any
z
x
of the signal in the sensitivity list. So reg needs to store the value until there is a change in sensitivity list.
LOGIC:
i
1.
i
4
o
e
state
i
unsigned
o
data
q
type
r
e
introduced
i
in
o
q
j
System
r
e
verilog.
2.System
i
Verilog
o
e
improves
i
the
o
classic
q
reg
r
e
data
i
type
o
q
j
so
r
e
that
i
it
o
can
q
be driven
z
by
i
o
e
a.
i
Continuous
o
assignments,
q
r
e
(ex:assign
i
crc=~crc;
o
q
j
r
e
i
o
)
i
o
e
b.
i
Gates,
o
(ex:
q
and
r
e
g1(q_out,
i
d);
o
q
j
)
www.testbench.in
i
o
e
c.
i
Modules,
o
(ex:
q
Flp_fops
r
e
f1
i
(q,
o
q
j
q_out,
r
e
clk,rst);
i
)
3.In
i
addition
o
e
to
i
being
o
a
q
variable.
r
e
It
i
is
o
q
j
given
r
e
the
i
synonym
o
logic
q
so that
z
it
u
y
does
e
o
not
z
x
look
i
o
e
i
like
o
a
q
register
r
e
declaration.
i
4.If
i
you
o
e
only
i
made
o
procedural
q
assignments
r
e
to
i
'logic'
o
q
j
then
r
e
it
i
was
o
semantically
q
equivalent to
z
'reg'.
u
y
5.A
i
logic
o
e
i
signal
o
can
q
be
r
e
used
i
anywhere
o
q
j
a
r
e
net
i
is
o
used,
q
except that
z
a
u
y
logic
e
o
variable
z
x
cannot be driven by
i
o
e
i
multiple
o
structural
q
drivers,
r
e
such
i
as
o
q
j
when
r
e
you
i
are
o
modeling
q
a bidirectional
z
bus.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
6.Example:
i
i
o
e
i
o
q
r
e
module
i
sample1
;
i
o
e
i
o
q
r
e
logic
i
crc
,
o
q
j
sa
r
e
,
d
,
i
q_out
;
i
o
e
i
o
q
r
e
logic
i
clk
,
rst
;
www.testbench.in
i
o
e
i
o
q
r
e
initial
i
o
e
i
o
q
r
e
begin
i
o
e
i
o
q
r
e
i
o
q
j
r
e
i
o
q
z
clk
=
1'b0
;
u
y
//procedural
e
o
assignment
i
o
e
i
o
q
r
e
i
o
q
j
r
e
i
o
q
#
10
z
clk
u
y
=
1'b1
;
i
o
e
i
o
q
r
e
end
i
o
e
i
o
q
r
e
assign
i
crc
=~
crc
;
o
q
j
r
e
i
o
//continuous
q
assignment
i
o
e
i
o
q
r
e
and
i
g1
(q_out,
o
q
j
d);
r
e
//q_out
i
is
o
driven
q
by gate
i
o
e
i
o
q
r
e
Flp_fops
i
f1
o
q
j
(q,
r
e
q_out,
i
clk,rst);
o
//q
q
is driven
z
by
u
y
module
i
o
e
i
o
q
r
e
endmodule
www.testbench.in
(Q
i
22)
o
e
What
i
is
o
the
q
need
r
e
of
i
clocking
o
q
j
blocks
r
e
?
Ans:
Any
i
signal
o
e
in
i
a
o
clocking
q
block
r
e
is
i
driven
o
q
j
or
r
e
sampled
i
synchronously,
o
ensuring
q
that your
z
testbench
u
y
interacts
e
o
with
z
x
the signals at the right time.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
The
i
"skew"
o
e
avoids
i
race
o
conditions
q
between
r
e
Testbench
i
and
o
q
j
DUT.
i
style="background-color:
o
e
#9cffff">
EXAMPLE:
i
o
clocking
i
cb
o
e
@(
posedge
i
clk
);
//
o
q
clocking
r
e
block
i
cb
o
q
j
declares,
r
e
signals
i
inside
o
r
q
active
z
on
u
y
e
o
positive
z
x
edge of clk.
i
o
e
i
o
q
r
e
i
o
q
j
r
e
i
o
q
default
input
z
u
y
#
1ns
e
o
output
z
x
#
2ns
;
// Input skew and output skew,
i
o
e
i
o
q
r
e
i
o
q
j
r
e
i
o
q
output
request
;
z
//output
u
y
from
e
o
z
x
DUT to testbench
www.testbench.in
i
o
e
i
o
q
r
e
i
o
q
j
r
e
i
o
q
input
z
grant
u
y
;
e
o
//Input
z
x
from testbench to DUT
endclocking
Note:
i
Iinput
o
e
signals(grant)
i
o
are
q
sampled
r
e
at
i
1ns
o
q
j
before
r
e
clock
i
event
o
and
q
output(request) are
z
driven
u
y
at
e
o
2ns
z
x
time after corresponding clock event
i
If
o
e
skew
i
is
o
not
q
specified,
r
e
default
i
input
o
q
j
skew
r
e
is
i
1step
o
and
q
output skew
z
is
u
y
0.
(Q
i
23)
o
e
What
i
are
o
the
q
ways
r
e
to
i
avoid
o
q
j
race
r
e
condition
i
between
o
test
q
bench and
z
RTL
u
y
using
e
o
z
x
SystemVerilog ?
Ans:
i
1)The
i
clock
o
e
which
i
is
o
given
q
to
r
e
DUT
i
and
o
q
j
Testbench
r
e
should
i
have
o
a
q
phase difference.
z
www.testbench.in
2)DUT
i
should
o
e
work
i
or
o
posedge
q
of
r
e
clock
i
and
o
q
j
testbench
r
e
should
i
work
o
on
q
negedge of
z
clock.
3)Testbench
i
output
o
e
and
i
DUT
o
output
q
pins
r
e
should
i
always
o
q
j
be
r
e
driven
i
using
o
non
q
blocking statements.
4)Clocking
i
blocks.
5)Program
i
block.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q
i
24)
o
e
Explain
i
Event
o
regions
q
in
r
e
SV
i
.
(Q
i
25)
o
e
What
i
are
o
the
q
types
r
e
of
i
coverages
o
q
j
available
r
e
in
i
SV
o
?
(Q
i
26)
o
e
Can
i
a
o
constructor
q
be
r
e
qualified
i
as
o
q
j
protected
r
e
or
i
local
o
in
q
SV ?
www.testbench.in
(Q
i
27)
o
e
How
i
to
o
have
q
a
r
e
#delay
i
statement
o
q
j
which
r
e
is
i
independent
o
of
q
timescale ?
z
I
u
y
verilog
e
o
,
z
x
the #delay is dependent on timescale.
(Q
i
28)
o
e
Is
i
it
o
possible
q
to
r
e
pass
i
struct
o
q
j
or
r
e
union
i
from
o
SV
q
to C
z
using
u
y
DPI
e
o
?
z
x
If yes, then how is it done ?
(Q
i
29)
o
e
What
i
is
o
OOPS?
(Q
i
30)
o
e
What
i
is
o
inheritance
q
?
(Q
i
31)
o
e
How
i
to
o
write
q
a
r
e
message
i
to
o
q
j
a
r
e
string
i
?
www.testbench.in
(Q
i
32)
o
e
Signals
i
inside
o
the
q
interface
r
e
should
i
be
o
q
j
wires
r
e
or
i
logic
o
?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q
i
33)
o
e
Give
i
examples
o
of
q
static
r
e
cast
i
and
o
q
j
dynamic
r
e
cast
i
.
(Q
i
34)
o
e
How
i
the
o
Static
q
cast
r
e
and
i
Dynamic
o
q
j
cast
r
e
errors
i
are
o
reported
q
?
(Q
i
35)
o
e
How
i
Parameterized
o
macros
q
can
r
e
be
i
debugged
o
q
j
?
(Q
i
36)
o
e
What
i
is
o
TLM
q
?
www.testbench.in
(Q
i
37)
o
e
What
i
will
o
be
q
the
r
e
values
i
of
o
q
j
rand
r
e
and
i
randc
o
variables
q
if randomization
z
fails
u
y
?
(Q
i
38)
o
e
Explain
i
about
o
the
q
r
e
Timeunit,
i
Timeprecision
o
q
j
and
r
e
`timescale
i
.
(Q
i
39)
o
e
Is
i
it
o
possible
q
to
r
e
access
i
a
o
q
j
member
r
e
of
i
a
o
struct
q
that is
z
returned
u
y
by
e
o
a
z
x
function in side the function ?
(Q
i
40)
o
e
How
i
to
o
randomize
q
a
r
e
real
i
data
o
q
j
type
r
e
variable
i
?
(Q
i
41)
o
e
What
i
is
o
$
q
in
r
e
SV
i
?
www.testbench.in
(Q
i
42)
o
e
What
i
are
o
the
q
types
r
e
of
i
parameterized
o
q
j
class?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q
i
43)
o
e
What
i
is
o
the
q
default
r
e
value
i
of
o
q
j
enumerated
r
e
data
i
type
o
?
(Q
i
44)
o
e
What
i
is
o
polymorphism
q
?
(Q
i
45)
o
e
Give
i
an
o
example
q
of
r
e
polymorphism
i
.
(Q
i
46)
o
e
What
i
are
o
the
q
types
r
e
of
i
polymorphism
o
q
j
?
www.testbench.in
(Q
i
47)
o
e
How
i
to
o
convert
q
a
r
e
command
i
line
o
q
j
defined
r
e
value
i
to
o
a
q
string in
z
SystemVerilog
u
y
?
(Q
i
48)
o
e
What
i
are
o
virtual
q
methods
r
e
?
(Q
i
49)
o
e
what
i
is
o
an
q
instance
r
e
of
i
a
o
q
j
class
r
e
?
(Q
i
50)
o
e
what
i
is
o
a
q
virtual
r
e
class?
(Q
i
51)
o
e
What
i
is
o
a
q
scope
r
e
resolution
i
operator?
www.testbench.in
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q
i
52)
o
e
What
i
is
o
deep
q
copy
r
e
?
(Q
i
53)
o
e
What
i
is
o
shallow
q
copy
r
e
?
(Q
i
54)
o
e
what
i
is
o
Method
q
Overloading?
(Q
i
55)
o
e
what
i
is
o
Method
q
OverRidingd?
(Q
i
56)
o
e
What
i
is
o
meant
q
by
r
e
abstraction?
www.testbench.in
(Q
i
57)
o
e
What
i
is
o
a
q
base
r
e
class?
i
(Q
i
58)
o
e
What
i
is
o
a
q
superclass?
r
e
(Q
i
59)
o
e
What
i
is
o
the
q
difference
r
e
between
i
Aggregation
o
q
j
and
r
e
Composition?
(Q
i
60)
o
e
What
i
is
o
the
q
need
r
e
of
i
virtual
o
q
j
interfaces
r
e
?
i
(Q
i
61)
o
e
What
i
are
o
the
q
advantages
r
e
of
i
OOP?
www.testbench.in
Ans:
Data
i
hiding
o
e
helps
i
create
o
secure
q
programs.
Redundant
i
code
o
e
can
i
be
o
avoided
q
by
r
e
using
i
inheritance.
Multiple
i
instances
o
e
of
i
objects
o
can
q
be
r
e
created.
Work
i
can
o
e
be
i
divided
o
easily
q
based
r
e
on
i
objects.
Inheritance
i
helps
o
e
to
i
save
o
time
q
and
r
e
cost.
(Q
i
62)
o
e
In
i
what
o
context
q
,
r
e
you
i
use
o
q
j
foreach
r
e
loop
i
?
(Q
i
63)
o
e
Write
i
code
o
to
q
r
e
print
i
the
o
q
j
contents
r
e
of
i
o
array_2d
q
[][] using
z
foreach
u
y
loop
e
o
?
www.testbench.in
(Q
i
64)
o
e
Implemented
i
code
o
to
q
merge
r
e
double
i
linked
o
q
j
list.
r
e
i
Define
o
each
q
element of
z
linked
u
y
list
e
o
using
z
x
class.
(Q
i
65)
o
e
What
i
will
o
the
q
printed
r
e
value
i
?
i
o
e
i
o
q
Bit
r
e
[
7
:
0
]
i
a
,
b
;
i
o
e
i
o
q
A
r
e
=
i
8
~Rhff
;
o
q
j
B
r
e
=
i
8
~Rh01
;
i
o
e
i
$display
(
"0"
,
A
o
+
q
B
);
(Q
i
66)
o
e
Why
i
checker...endchecker
o
is
q
used
r
e
?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
www.testbench.in
(Q
i
67)
o
e
I
i
want
o
to
q
delay
r
e
simulation
i
by
o
q
j
smallest
r
e
unit
i
of
o
time.
q
i.e minimum
z
of
u
y
all
e
o
the
z
x
timeprecision. How to do it ?
(Q
i
68)
o
e
Explain
i
stratified
o
event
q
queue
r
e
?
(Q
i
69)
o
e
Define
i
enumerated
o
data
q
type
r
e
,with
i
one
o
q
j
of
r
e
its
i
elements
o
value
q
to be
z
X.
(Q
i
70)
o
e
Is
i
this
o
a
q
valid
r
e
syntax
i
?
enum
i
{
a
=
0
,
o
e
b
=
7
,
i
c
,
o
d
=
8
}
q
alphabet
;
(Q
i
71)
o
e
What
i
are
o
the
q
different
r
e
types
i
of
o
q
j
parameters
r
e
available
i
in
o
SV?
www.testbench.in
(Q
i
72)
o
e
What
i
is
o
the
q
use
r
e
of
i
"type"
o
q
j
operator
r
e
?
(Q
i
73)
o
e
What
i
type
o
is
q
the
r
e
index
i
for
o
q
j
int
r
e
array_name
i
[*]?
o
(Q
i
74)
o
e
In
i
a
o
Array,
q
If
r
e
i
index
o
q
j
is
r
e
out
i
of
o
the
q
address bounds,
z
then
u
y
what
e
o
will
z
x
be the return value ?
(Q
i
75)
o
e
What
i
is
o
the
q
return
r
e
type
i
of
o
q
j
Array
r
e
locator
i
method
o
find_index
q
?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q
i
76)
o
e
Write
i
a
o
program
q
to
r
e
choose
i
elements
o
q
j
randomly
r
e
from
i
Queue.
o
No
q
element should
z
be
u
y
reputed
e
o
until
z
x
all elements are chosen. Queue may have elements repeated.
www.testbench.in
(Q
i
77)
o
e
Declare
i
a
o
queue
q
of
r
e
integers
i
with
o
q
j
maximum
r
e
number
i
of
o
elements
q
to 256.
(Q
i
78)
o
e
Explain
i
how
o
you
q
debugged
r
e
randomization
i
failure.
(Q
i
79)
o
e
What
i
is
o
zero
q
delay
r
e
loop
i
and
o
q
j
What
r
e
is
i
the
o
problem
q
with zero
z
delay
u
y
loop
e
o
?
(Q
i
80)
o
e
What
i
is
o
the
q
difference
r
e
between
i
zero
o
q
j
delay
r
e
loop
i
in
o
design
q
and testbench
z
?
(Q
i
81)
o
e
Is
i
randomize()
o
method
q
is
r
e
virtual
i
?
www.testbench.in
(Q
i
82)
o
e
Write
i
code
o
for
q
the
r
e
below
i
spec:
o
q
j
i
o
e
i
o
q
r
e
i
2
o
q
j
varibles
r
e
a,b
i
are
o
declared
q
in module.
z
i
o
e
i
o
q
r
e
i
Generate
o
q
j
random
r
e
runbers
i
such
o
that
q
a >
z
b.
u
y
i
o
e
i
o
q
r
e
i
Do
o
q
j
not
r
e
use
i
$random
o
or
q
$urandom.
(Q
i
83)
o
e
In
i
a
o
class,
q
a
r
e
variable
i
is
o
q
j
declared
r
e
as
i
randc.
o
But
q
when randomized,
z
the
u
y
random
e
o
value
z
x
doesn~Rt seem to be cyclic. What could be the reason ?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q
i
84)
o
e
Pre_randomize()
i
is
o
virtual
q
or
r
e
not
i
?
i
o
e
i
o
q
r
e
i
If
o
q
j
"yes",
r
e
did
i
you
o
use
q
the keyword
z
"virtual"
u
y
in
e
o
front
z
x
of pre_randomize() ?
www.testbench.in
i
o
e
i
o
q
r
e
i
If
o
q
j
"not",
r
e
then
i
what
o
about
q
the pre_randomize()
z
definition
u
y
defined
e
o
in
z
x
extended class ?
(Q
i
85)
o
e
How
i
to
o
generate
q
random
r
e
numbers
i
bw
o
q
j
a
r
e
range
i
of
o
values?
Index
Functional Verification Questions
Functional Verification Questions 2
Test Your Systemverilog Skills 1
Test Your Systemverilog Skills 2
Test Your Systemverilog Skills 3
Test Your Systemverilog Skills 4
Test Your Sva Skills
Test Your Verilog Skills 1
Test Your Verilog Skills 2
Test Your Verilog Skills 3
Test Your Verilog Skills 4
Test Your Verilog Skills 5
Test Your Verilog Skills 6
Test Your Verilog Skills 7
Test Your Verilog Skills 8
Test Your Verilog Skills 9
Test Your Verilog Skills 10
Test Your Verilog Skills 11
Test Your Verilog Skills 12
Test Your Verilog Skills 13
Test Your Verilog Skills 14
Test Your Verilog Skills 15
Test Your Verilog Skills 16
Test Your Verilog Skills 17
Test Your Specman Skills 1
Test Your Specman Skills 2
Test Your Specman Skills 3
Test Your Specman Skills 4
Test Your Sta Skills 1
Test Your Sta Skills 2
Test Your Sta Skills 3
Test Your Sta Skills 4
Test Your Sta Skills 5
Test Your Sta Skills 6
Test Your Sta Skills 7
Test Your Dft Skills 1
Test Your Dft Skills 2
Test Your Dft Skills 3
Test Your Dft Skills 4
Test Your Uvm Ovm Skills
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