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TEST YOUR SYSTEMVERILOG SKILLS 4


(Q i159)o eWhati wouldobe qthere output iofoq jthere following icode oandqhow toz avoidu yite o?
for i(into ei=0;i i<N;oi++) qbegin
io ei o qre ioq jfork
io ei o qre ioq jre iint ojq= i;
io ei o qre ioq jre ibegin
io ei o qre ioq jre i o#10q$display(" Jz valueu yise o0zx ",j);
io ei o qre ioq jre iend
io ei o qre ioq jjoin_none
io ei o qre end www.testbench.in


J iiso ealwaysi No, qByre using iautomaticoq jKeyre word, iThis oproblemqcan bez avoidedu y.
for i(into ei=0;i i<N;oi++) qbegin
io ei o qre ioq jfork
io ei o qre ioq jre iautomatic ointqj =z i;
io ei o qre ioq jre ibegin
io ei o qre ioq jre i o#10q$display(" Jz valueu yise o0zx ",j);
io ei o qre ioq jre iend
io ei o qre ioq jjoin_none .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n

io ei o qre end www.testbench.in


(Q i160)o eIsi itopossible qforre a ifunctionoq jtore return ia oarray(qmemory) ?

(Q i161)o eHowi toocheck qwhetherre randomization iisoq jsuccessfulre or inot?

(Q i162)o eDoi weoneed qtore call isuper.new()oq jwhenre extending ia oclassq? Whatz happensu yife owezx don't call ?

(Q i163)o eWhati isothe qneedre to iimplementoq jexplicitlyre a icopy() omethodqinside az transactionu y,e owhenzx we can simple assign one object to other ?

(Q i164)o eHowi differentois qthere implementation iofoq jare struct iand ounionqin SV.z www.testbench.in


(Q i165)o eWhati iso"this" q?

(Q i166)o eWhati isotagged qunionre ?

(Q i167)o eWhati iso"scope qresolutionre operator" i?

(Q i168)o eWheni aoSequence qMatches? .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n


(Q i169)o eWhati isoa qProperty? www.testbench.in


(Q i170)o eWhati isothe qdifferencere between iVerilogoq jParameterizedre Macros iand oSystemVerilogqParameterized Macrosz ?

(Q i171)o eWhati isothe qdifferencere between i
ilogico edata_1;
ivaro elogici data_2;
iwireo elogici data_3o;
ibito edata_4;
ivaro ebiti data_5;
www.testbench.in

(Q i172)o eWhati isothe qdifferencere between ibitoq jandre logic i?

(Q i173)o eWritei aoState qmachinere in iSVoq jstylere .

(Q i174)o eWhati isoadvantage qofre program iblockoq joverre clock iblocks ow.r.tqrace conditionz ?

(Q i175)o eHowi tooavoid qthere race iconditionoq jbetweenre 2 iprogram oblockq? .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n


(Q i176)o eWhati isocoverage qdrivenre verification i?
www.testbench.in

(Q i177)o eWhati isolayered qarchitecturere ?

(Q i178)o eWhati areothe qsimulationre phases iinoq jyourre verification ienvironment o?

(Q i179)o eHowi toopick qare element iwhichoq jisre in iqueue ofromqrandom indexz ?

(Q i180)o eWhati dataostructure qisre used itooq jstorere data iin oyourqenvironment andz whyu y?

(Q i181)o eWhati isocasting q?re Explain iaboutoq jthere various itypes oofqcasting availablez inu ySVe o.
www.testbench.in

(Q i182)o eHowi tooimport qallre the iitemsoq jdeclaredre inside ia opackageq?

(Q i183)o eExplaini howothe qtimescalere unit iandoq jprecisionre are itaken owhenqa modulez doesu ynote ohavezx any timescale declaration in RTL ?

(Q i184)o eWhati isostreaming qoperatorre and iwhatoq jisre its iuse o?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n

(Q i185)o eWhati areovoid qfunctionsre ?

(Q i186)o eHowi toomake qsurere that iaoq jfunctionre argument ipassed oasqref isz notu ychangede obyzx the function ?
www.testbench.in

(Q i187)o eWhati isothe qusere of i"extern"oq j?

(Q i188)o eWhati isothe qdifferencere between iinitialoq jblockre and ifinal oblock?
Ans:


io ei Youocan't qschedulere an ieventoq jorre have idelays oinqfinal block.



(Q i189)o eHowi toocheck qwhetherre a ihandleoq jisre holding iobject oorqnot ?

(Q i190)o eHowi toodisable qmultiplere threads iwhichoq jarere spawned iby ofork...joinq
www.testbench.in
Index
Functional Verification Questions
Functional Verification Questions 2
Test Your Systemverilog Skills 1
Test Your Systemverilog Skills 2
Test Your Systemverilog Skills 3
Test Your Systemverilog Skills 4
Test Your Sva Skills
Test Your Verilog Skills 1
Test Your Verilog Skills 2
Test Your Verilog Skills 3
Test Your Verilog Skills 4
Test Your Verilog Skills 5
Test Your Verilog Skills 6
Test Your Verilog Skills 7
Test Your Verilog Skills 8
Test Your Verilog Skills 9
Test Your Verilog Skills 10
Test Your Verilog Skills 11
Test Your Verilog Skills 12
Test Your Verilog Skills 13
Test Your Verilog Skills 14
Test Your Verilog Skills 15
Test Your Verilog Skills 16
Test Your Verilog Skills 17
Test Your Specman Skills 1
Test Your Specman Skills 2
Test Your Specman Skills 3
Test Your Specman Skills 4
Test Your Sta Skills 1
Test Your Sta Skills 2
Test Your Sta Skills 3
Test Your Sta Skills 4
Test Your Sta Skills 5
Test Your Sta Skills 6
Test Your Sta Skills 7
Test Your Dft Skills 1
Test Your Dft Skills 2
Test Your Dft Skills 3
Test Your Dft Skills 4
Test Your Uvm Ovm Skills

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