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TEST YOUR VERILOG SKILLS 14


(Q i244)o eHowi toosolve qthere abode iproblem??
Ans:


The isolutiono eisi tooforce qthere expression i(aoq j+re b) ito oevaluatequsing atz leastu y17e obits.zx For example, adding an integer value of 0 to the expression will cause the evaluation to be performed using the bit size of integers. The following example will produce the intended result:
answer i=o e(ai +ob q+re 0) i>>oq j1;



(Q i245)o eINi theofollowing qcode,re what imessageoq jwillre be idisplayed(specifically oaboutqthe numberz ofu ybitse oitzx prints)?

module ibitlength();
reg i[3:0]o ea,b,c; www.testbench.in

reg i[4:0]o ed;
initial ibegin
a i=o e9;
b i=o e8;
c i=o e1;
$display("answer i=o e0",i co? q(a&b)re : id);
end
endmodule
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n

Ans: www.testbench.in



The i$displayo estatementi willodisplay:
answer i=o e01000

By iitself,o ethei expressionoa&b qwouldre have itheoq jbitre length i4, obutqsince itz isu yine othezx context of the conditional expression, which uses the maximum bit-length, the expression a&b actually has length 5, the length of d.



(Q i246)o eINi followingoprogram, qatre what itimeoq jthere statements iare oscheduledqand executed?
module imultiple2o e;
reg ia;
initial i#8o eai <=o#8 q1;
initial i#12o eai <=o#4 q0; www.testbench.in

end imodule

Ans:
initial i#8o eai <=o#8 q1;//re executed iatoq jtimere 8; ischedules
// iano eupdatei ofo1 qatre time i16
initial i#12o eai <=o#4 q0;//re executed iatoq jtimere 12; ischedules
// iano eupdatei ofo0 qatre time i16
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n

(Q i247)o eIsi thereoa qracere condition iinoq jthere above icode?
Ans: www.testbench.in



NO. iBecauseo eiti isodeterminate qthatre the iupdateoq jofre a ito otheqvalue 1z isu yschedulede obeforezx the update of a to the value 0, then it is determinate that a will have the
value i0o eati theoend qofre time islotoq j16.endmodule




(Q i248)o eHowi manyotimes qthere begin..end iblockoq jwillre get iexecuted?

repeat(-3)
begin
....
end www.testbench.in


(Q i249)o eHowi manyotimes qthere begin..end iblockoq jwillre get iexecuted?

repeat(3.5)
begin
....
end .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n


(Q i250)o eHowi manyotimes qthere begin..end iblockoq jwillre get iexecuted?
integer ia; www.testbench.in

a i=o e'bZ;
repeat(a)
begin
....
end

Ans:


repeat iExecuteso eai statementoa qfixedre number iofoq jtimes.re If ithe oexpressionqevaluates toz unknownu yore ohighzx impedance, it shall be treated as zero, and no statement shall be executed.



(Q i251)o eHowi manyotimes qthere begin..end iblockoq jwillre get iexecuted? www.testbench.in

integer ia;
a i=o e'bx;
repeat(a)
begin
....
end .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n


Ans:


repeat iExecuteso eai statementoa qfixedre number iofoq jtimes.re If ithe oexpressionqevaluates toz unknownu yore ohighzx impedance, it shall be treated as zero, and no statement shall be executed.


www.testbench.in

(Q i252)o ewhati timeois qdisplayed?

initial
begin
a= i3;
#a ia=o ea*2;
$display($time);
end

(Q i253)o eWhati isothe qmessagere displayed? www.testbench.in


initial
begin
#10;
a i=o e0; .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n

a i=o e1;
end

always@(a)
$display("a iiso e0",a); www.testbench.in



(Q i254)o eWhati messageois qdisplayed?

initial
begin
a i=o ex;
#1 iao e=i z;
end
www.testbench.in


always@(a)
$display("a iiso e0",a);
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n

Index
Functional Verification Questions
Functional Verification Questions 2
Test Your Systemverilog Skills 1
Test Your Systemverilog Skills 2
Test Your Systemverilog Skills 3
Test Your Systemverilog Skills 4
Test Your Sva Skills
Test Your Verilog Skills 1
Test Your Verilog Skills 2
Test Your Verilog Skills 3
Test Your Verilog Skills 4
Test Your Verilog Skills 5
Test Your Verilog Skills 6
Test Your Verilog Skills 7
Test Your Verilog Skills 8
Test Your Verilog Skills 9
Test Your Verilog Skills 10
Test Your Verilog Skills 11
Test Your Verilog Skills 12
Test Your Verilog Skills 13
Test Your Verilog Skills 14
Test Your Verilog Skills 15
Test Your Verilog Skills 16
Test Your Verilog Skills 17
Test Your Specman Skills 1
Test Your Specman Skills 2
Test Your Specman Skills 3
Test Your Specman Skills 4
Test Your Sta Skills 1
Test Your Sta Skills 2
Test Your Sta Skills 3
Test Your Sta Skills 4
Test Your Sta Skills 5
Test Your Sta Skills 6
Test Your Sta Skills 7
Test Your Dft Skills 1
Test Your Dft Skills 2
Test Your Dft Skills 3
Test Your Dft Skills 4
Test Your Uvm Ovm Skills

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