This testbench is developed in VMM (Systemverilog) for the Ethernet core available from opencores.org. My intension here is to explore the VMM methodology but not to verify the Ethernet core, as a result there are many bugs in the environment. I dont remember the versions of VMM but I developed these in the third quarter of 2007. To simulate this testbench some dependencies on libraries has to be removed from RTL files. It takes bit time for these changes in RTL.
Full support of automatic random, constrained random, and directed testcase creation.
Supports injuction of random errored packets.
Supports 1G Fullduplex modeled both in RX and TX paths.
Protocol Checker/Monitor for self checking.
Built in function coverage support for packets.
Developed in Systemverilog using Synopsys VMM base classes.
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