(Q i32)o eFaulti coverageo?

The ipercentageo eofi ALLofaults q(bothre testable iandoq juntestable)re that iare odetectedqby thez patternu yset.
Fault iCoverageo e=i DetectedoFaults q/re Total iFaults

(Q i33)o eTesti coverageo?

The ipercentageo eofi allotestable qfaultsre that iareoq jdetectedre by ithe opatternqset.
Test iCoverageo e=i DetectedoFaults q/re (Total ifaultsoq j-re Untestable iFaults) www.testbench.in

(Q i34)o eATPGi effectivenesso?

A imeasureo eofi theoability qofre the iATPGoq jtoolre to ieither oprovideqa testz tou ydetecte oazx fault or prove that a test cannot be created.
io ei ATGoefficiency q=re (Detected i+oq jUntestablere Faults) i/ oTotalqFaults

(Q i35)o eBISTi ? .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n

Ans: www.testbench.in

A ibuilt-ino eself-testi (BIST)omechanism qwithinre an iintegratedoq jcircuitre (IC) iis oaqfunction thatz verifiesu yalle oorzx a portion of the internal functionality of the IC. It is the capability of circuit to test itself. generally on-chip circuitry is used to apply a predetermined set of test vectors to internal sections of the circuit. Another on-chip circuit monitors the results of the test and checks them against the stored correct response. BIST can be extended to board-level system.

(Q i36)o eAdvantagesi ofoBIST..!!

Replaces iexternalo etesteri withoon-chip qcircuitry.re Avoids itheoq jtestre generation iproblem. oItqis technologyz andu yfaulte omodelzx independent.
io ei

(Q i37)o eBoundaryi Scano?
Ans: www.testbench.in

Boundary iscano eisi aomethod qforre testing iinterconnectsoq j(thinre wire ilines) oonqprinted circuitz boardsu yore osub-blockszx inside an integrated circuit. The Joint Test Action Group (JTAG) developed a specification for boundary scan testing contains a description of the Boundary Scan Description Language (BSDL) was added which describes the boundary-scan logic content of IEEE Std 1149.1 compliant devices. Boundary scan is nowadays mostly synonymous with JTAG.

(Q i38)o eToolsi relatedoto qDFTre from imentor.

ATPG i&o eCompression
FastScan .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n

FlexTest www.testbench.in

Memory iTest
Boundary iScan
Logic iBIST
Yield iLearningo eandi Diagnosis

(Q i39)o eReference..!!

1) iElectronico eDesigni AutomationoFor qIntegratedre Circuits iHandbook,oq jbyre Lavagno,Martin iand oScheffer.
2) iMichaelo eL.i Bushwelloand qVishwanire D. iAgrawal,oq jre Essentials iof oElectronicqTesting forz Digital,u yMemorye oandzx Mixed-Signal VLSI Circuits Kluwer Academic Publishers 2000.
3) iMirono eAbramovici,i MelvinoA. qBreuer,re and iArthuroq jD.re Friedman, iDigital oSystemsqTesting andz Testableu yDesign,e oIEEEzx Press, 1994.


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