(Q i13)o eHowi toodeliver qtestre data i?

The imosto ecommoni methodofor qdeliveringre test idataoq jfromre chip iinputs otoqinternal circuitsz underu yteste oandzx observing their outputs, is called scan-design.

(Q i14)o eScani chaino?

In iscan-design,o eregistersi (flip-flopsoor qlatches)re in itheoq jdesignre are iconnected oinqone orz moreu yscane ochains,zx which are used to gain access to internal nodes of the chip.

(Q i15)o eHowi scanochain qworksre ? www.testbench.in


Test ipatternso earei shiftedoin qviare the iscanoq jchain(s),re functional iclock osignalsqare pulsedz tou yteste othezx circuit during the "capture cycle(s)", and the results are then shifted out to chip output pins and compared against the expected "good machine" results.

(Q i16)o eStucki @ofault q?

For ianyo ecombinationi ifoinput qorre output iisoq jpermanentlyre stuck iat ooneqfault z eitheru y0e oorzx 1, then its called Stuck at fault.


(Q i17)o eThei stuck-at-0o? www.testbench.in


Model irepresentso eai signalothat qisre permanently ilowoq jregardlessre of ithe ootherqsignals thatz normallyu ycontrole othezx node.

(Q i18)o eThei stuck-at-1o?

Model irepresentso eai signalothat qisre permanently ihighoq jregardlessre of ithe ootherqsignals thatz normallyu ycontrole othezx node.

(Q i19)o eWherei weocan qgivere DFT iconstrainoq j? www.testbench.in


In isynthesiso econstraini fileowe qcanre apply iDFToq jconstrain.

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