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Specman E
Interview Questions
TEST YOUR VERILOG SKILLS 15
(Q
i
255)
o
e
What
i
message
o
is
q
displayed?
initial
begin
a
i
=
o
e
x;
#1
i
a
o
e
=
i
1;
end
www.testbench.in
always@(posedge
i
a)
$display("
posedge
i
on
o
e
a
i
is
o
seen
");
(Q
i
256)
o
e
What
i
is
o
the
q
equivalent
r
e
always@(*)
i
in
o
q
j
the
r
e
following
i
program?
always
i
@(*)
o
e
y
i
=
o
e
(a
i
&
o
b)
q
|
r
e
(c
i
&
o
q
j
d)
r
e
|
i
myfunction(f);
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Ans:
www.testbench.in
equivalent
i
to
o
e
@(a
i
or
o
b
q
or
r
e
c
i
or
o
q
j
d
r
e
or
i
f)
(Q
i
257)
o
e
What
i
is
o
the
q
equivalent
r
e
always@(*)
i
in
o
q
j
the
r
e
following
i
program?
always
i
@*
o
e
begin
i
tmp1
i
=
o
e
a
i
&
o
b;
tmp2
i
=
o
e
c
i
&
o
d;
y
i
=
o
e
tmp1
i
|
o
tmp2;
www.testbench.in
end
Ans:
equivalent
i
to
o
e
@(a
i
or
o
b
q
or
r
e
c
i
or
o
q
j
d
r
e
or
i
tmp1
o
or
q
tmp2)
(Q
i
258)
o
e
What
i
is
o
the
q
equivalent
r
e
@(*)
i
in
o
q
j
the
r
e
following
i
program?
always
i
@*
o
e
begin
i
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
x
i
=
o
e
a
i
^
o
b;
@(*)
www.testbench.in
x
i
=
o
e
c
i
^
o
d;
end
Ans:
(Q
i
259)
o
e
What
i
is
o
the
q
equivalent
r
e
always@(*)
i
in
o
q
j
the
r
e
following
i
program?
always
i
@*
o
e
begin
i
y
i
=
o
e
8'hff;
www.testbench.in
y[a]
i
=
o
e
!en;
end
Ans:
equivalent
i
to
o
e
as
i
@(a
o
or
q
en)
(Q
i
260)
o
e
Whether
i
non
o
bocking
q
statements
r
e
are
i
allowed
o
q
j
in
r
e
function?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Ans:
No.
i
Non
o
e
Blocking
i
statements
o
are
q
not
r
e
allowed
i
in
o
q
j
function.
www.testbench.in
(Q
i
261)
o
e
i
Maximum
o
number
q
files
r
e
can
i
be
o
q
j
opened
r
e
using
i
fopen
o
?
(Q
i
262)
o
e
Whether
i
non
o
blocking
q
statements
r
e
are
i
allowed
o
q
j
in
r
e
automatic
i
task?
Because
i
variables
o
e
declared
i
in
o
automatic
q
tasks
r
e
are
i
deallocated
o
q
j
at
r
e
the
i
end
o
of
q
the task
z
invocation,
u
y
they
e
o
shall
z
x
not be used in certain constructs like nonblocking that might refer to them after that point.
(Q
i
263)
o
e
Is
i
it
o
possible
q
to
r
e
see
i
the
o
q
j
automatic
r
e
task
i
local
o
variables
q
in waveform
z
debugger?
Ans:
No
i
it
o
e
is
i
not
o
possible
q
to
r
e
see.
i
These
o
q
j
variables
r
e
are
i
automatically
o
deallocated
q
at the
z
end
u
y
of
e
o
task
z
x
invocation.
(Q
i
264)
o
e
Is
i
it
o
possible
q
to
r
e
use
i
automatic
o
q
j
task
r
e
local
i
variables
o
in
q
$monitor?
www.testbench.in
Ans:
No
i
.
o
e
These
i
variables
o
are
q
automatically
r
e
deallocated
i
at
o
q
j
the
r
e
end
i
of
o
task
q
invocation.
(Q
i
265)
o
e
Is
i
it
o
possible
q
to
r
e
use
i
procedural
o
q
j
continuous
r
e
assignments
i
or
o
procedural
q
force statements
z
on
u
y
automatic
e
o
task
z
x
local variables?
Ans:
No.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q
i
266)
o
e
Is
i
it
o
possible
q
to
r
e
disable
i
a
o
q
j
function?
Ans:
A
i
function
o
e
cannot
i
be
o
disables.
q
The
r
e
disable
i
statement
o
q
j
can
r
e
be
i
used
o
to
q
disable named
z
blocks
u
y
within
e
o
a
z
x
function. In cases where a disable statement within a function disables a block or a task that called the function, the behavior is undefined.
www.testbench.in
(Q
i
267)
o
e
Between
i
the
o
if-else
q
and
r
e
case
i
statements
o
q
j
which
r
e
is
i
usually
o
preferred?
Ans:
Case
i
is
o
e
better
i
from
o
synthesis
q
point
r
e
of
i
view.
if
i
else
o
e
will
i
be
o
synthesized
q
to
r
e
a
i
priority
o
q
j
encoder.
Whereas
i
case
o
e
will
i
be
o
synthesized
q
to
r
e
a
i
normal
o
q
j
encoder.
Priority
i
encoder
o
e
has
i
more
o
gates
q
and
r
e
also
i
timing
o
q
j
is
r
e
affected.
So,case
i
is
o
e
usually
i
preferred.
www.testbench.in
There
i
are
o
e
switches
i
that
o
design
q
compiler(synopses
r
e
synthesis
i
tool)
o
q
j
provides
r
e
to
i
synthesize
o
case
q
statement either
z
way.
Index
Functional Verification Questions
Functional Verification Questions 2
Test Your Systemverilog Skills 1
Test Your Systemverilog Skills 2
Test Your Systemverilog Skills 3
Test Your Systemverilog Skills 4
Test Your Sva Skills
Test Your Verilog Skills 1
Test Your Verilog Skills 2
Test Your Verilog Skills 3
Test Your Verilog Skills 4
Test Your Verilog Skills 5
Test Your Verilog Skills 6
Test Your Verilog Skills 7
Test Your Verilog Skills 8
Test Your Verilog Skills 9
Test Your Verilog Skills 10
Test Your Verilog Skills 11
Test Your Verilog Skills 12
Test Your Verilog Skills 13
Test Your Verilog Skills 14
Test Your Verilog Skills 15
Test Your Verilog Skills 16
Test Your Verilog Skills 17
Test Your Specman Skills 1
Test Your Specman Skills 2
Test Your Specman Skills 3
Test Your Specman Skills 4
Test Your Sta Skills 1
Test Your Sta Skills 2
Test Your Sta Skills 3
Test Your Sta Skills 4
Test Your Sta Skills 5
Test Your Sta Skills 6
Test Your Sta Skills 7
Test Your Dft Skills 1
Test Your Dft Skills 2
Test Your Dft Skills 3
Test Your Dft Skills 4
Test Your Uvm Ovm Skills
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