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TEST YOUR VERILOG SKILLS 5


(Q i91)o ei Toomodify qare behavioral iVerilogoq jwaitre statement ito omakeqit synthesizedz

Original
icode:
command1
;
wait i(xo e!=i 0);
command3
;

Ans:
www.testbench.in

Synthesized iVerilog:
case i(state)
io e0i :obegin
io ei o qre ioq jcommand1;
io ei o qre ioq jifre (x i!= o0)qcommand3;
io ei o qre ioq jelsere state i<= o1;
io ei o qre end

io e1i :oif q(xre != i0)oq j//re wait iuntil othisqis true .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n

io ei o qre ioq jcommand3; www.testbench.in

endcase


(Q i92)o ei Whatoare qthere types iofoq jracere conditions?

(Q i93)o ei Howoto qavoiderre race iconditionoq jbetweenre dut iand otestbench?

(Q i94)o ei Giveothe qguidere lines iwhichoq javoidsre race icondition.

(Q i95)o ei Whatois qthere use iofoq jlintingre tool? www.testbench.in


(Q i96)o ei Writeothe qcodere to iinstantiatedoq j1kre "and igates" oinqa module.z


(Q i97)o ei Whatois qconfigurationre block?
Ans:


Verilog-2000 iaddso econfigurationi blocks,owhich qallowre the iexactoq jversionre and isource olocationqof eachz Verilogu ymodulee otozx be specified as part of the Verilog language. For portability, virtual model libraries are used in configuration blocks, and separate library map files associate virtual libraries with physical locations. Configuration blocks are specified outside of module definitions.


.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n

(Q i98)o ei Howomany qfilesre can ibeoq jopened(withoutre closing) iusing omultichannelqdescriptor ?
Ans: www.testbench.in

31 ifiles.

(Q i99)o ei Whyoonly q31re files icanoq jbere opened(without iclosing) ousingqmultichannel descriptorz whileu yintegere ocanzx hole 32 bits?
Ans:


The imosto esignificanti bito(bit q32)re of iaoq jmultire channel idescriptor oisqreserved, andz shallu yalwayse obezx cleared, limiting an implementation to at most 31 files opened for output via multi channel descriptors.



(Q i100)o ei Ifomcd(multichannel qdescriptor)re is i00000000000000000000000000001oq j,re then iwhat odoesqit mean?
Ans:


The ileasto esignificanti bito(bit q0)re of iaoq jmcdre always irefers otoqthe standardz output.


www.testbench.in

(Q i101)o eWhichi isobetter qtore use iwhenoq jcreatingre test ivectors? o$displayqor $strobe?

(Q i102)o eHowi wouldoyou qcaterre with iopeningoq j35re files?


(Q i103)o eWhati areothe qtypicalre tasks iyouoq jperformre inside ia ospecifyqblock?
Ans: .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n



- iDescribeo evariousi pathsoacross qthere module iandoq jassignre delays ito othoseqpaths.
- iDescribeo etimingi checksoto qensurere that itheoq jtimingre constraints iof otheqdevice arez met.
- iDefineo ethei pulseofiltering qlimitsre for iaoq jspecificre module ior oforqparticular pathsz withinu yae omodule. www.testbench.in




(Q i104)o ei Findothe qbugre in itheoq jfollowingre code.

always@(posedge iclk)
a
i=o eb;
always@(posedge iclk)
b
i=o ea;

(Q i105)o ei Findothe qbugre in itheoq jfollowingre code.
www.testbench.in

if i(a=b)
match
i=o e1;
else
match
i=o e0;

Ans: .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n



if(a=b) iassignso ebi tooa, qthenre if iaoq jisre non-zero isets omatch.qThe correctz codeu yis
iifo e(a==b)i
match i=o e1;
else www.testbench.in

match i=o e0;


Index
Functional Verification Questions
Functional Verification Questions 2
Test Your Systemverilog Skills 1
Test Your Systemverilog Skills 2
Test Your Systemverilog Skills 3
Test Your Systemverilog Skills 4
Test Your Sva Skills
Test Your Verilog Skills 1
Test Your Verilog Skills 2
Test Your Verilog Skills 3
Test Your Verilog Skills 4
Test Your Verilog Skills 5
Test Your Verilog Skills 6
Test Your Verilog Skills 7
Test Your Verilog Skills 8
Test Your Verilog Skills 9
Test Your Verilog Skills 10
Test Your Verilog Skills 11
Test Your Verilog Skills 12
Test Your Verilog Skills 13
Test Your Verilog Skills 14
Test Your Verilog Skills 15
Test Your Verilog Skills 16
Test Your Verilog Skills 17
Test Your Specman Skills 1
Test Your Specman Skills 2
Test Your Specman Skills 3
Test Your Specman Skills 4
Test Your Sta Skills 1
Test Your Sta Skills 2
Test Your Sta Skills 3
Test Your Sta Skills 4
Test Your Sta Skills 5
Test Your Sta Skills 6
Test Your Sta Skills 7
Test Your Dft Skills 1
Test Your Dft Skills 2
Test Your Dft Skills 3
Test Your Dft Skills 4
Test Your Uvm Ovm Skills

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