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TEST YOUR VERILOG SKILLS 16
(Q i268)o ei Whatois qmutex?
(Q i269)o ei Howoto qmodelre a imutexoq jinre verilog? i
(Q i270)o eWhati isosemaphore?
(Q i271)o eHowi toomodel qare semaphore iinoq jverilog?
www.testbench.in
(Q i272)o eWhati isothe qdifferencere between imutexoq jandre semaphore?
(Q i273)o eHowi toodisplay qthere messages iinoq jcolorful?
Ans:
The ifollowingo eprogrami showsohow qtore display imessagesoq jinre colorful.
This iworkso eonlyi inoASIC qTerminals.
Simulate itheo efollowingi codeoin qLinuxre or iUnixoq jandre see ithe ooutputs.
module iasdsadf();
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
initial www.testbench.in
begin
$write("^@[1;34m",27);
$display("***********| io e0|i |o| q|re | i|oq j|re | i oThisqis inz blueu y***********",e o1);
$write("^@[0m",27);
$display("^@[1;31m",27); i
$display("***********| io e0|i |o| q|re | i|oq j|re | i oThisqis inz redu y***********",e o2);
$display("^@[0m",27);
$display("^@[0;33m",27); www.testbench.in
$display("**********| io e0|i |o| q|re | i|oq j|re | i oThisqis inz pendau ycolore o***********",zx 3);
$display("^@[0m",27);
$display("^@[5;34m",27);
$display("***********| io e0|i |o| q|re | i|oq j|re | i oThisqis inz Blinku y***********",e o4);
$display("^@[0m",27); i
$display("^@[7;34m",27); i .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
$display("***********| io e0|i |o| q|re | i|oq j|re | i oThisqis inz Backu ygrounde ocolorzx ***********", 1);
$display("^@[0m",27); www.testbench.in
end
endmodule
(Q i274)o eWhati isoTOP qmodule?
Ans:
Top-level imoduleso earei modulesothat qarere included iinoq jthere source itext obutqare notz instantiated.u ye ozx In verification environment, the highest module in the huarache is generally named as top.
www.testbench.in
(Q i275)o eHowi toodeclare qrealre numbers iasoq jports?
Ans:
Real inumbero earei allowedoto qbere declared iasoq jports.re To iuse orealqnumbers asz ports,u yusee o$bitstorealzx and $realtobits.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i276)o eWheni isofork-join qused?
www.testbench.in
(Q i277)o eWhichi proceduraloassignment qshouldre be iusedoq jtore model ia ocombinatorialqlogic buffer?
1)
always i@(in)
#5 iouto e=i in;
2)
always i@(in)
#5 iouto e<=i in;
www.testbench.in
3)
always i@(in)
out i=o e#5i in;
4)
always i@(in) .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
out i<=o e#5i in;
(Q i278)o eWhichi proceduraloassignment qshouldre be iusedoq jtore model ia osequentialqlogic flip-flop?
www.testbench.in
1)
always i@(posedgeo eclk)
#5 iqo e=i d;
2)
always i@(posedgeo eclk)
#5 iqo e<=i d;
3)
always i@(posedgeo eclk) www.testbench.in
q i=o e#5i d;
4)
always i@(posedgeo eclk)
q i<=o e#5i d; .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i279)o eExplorei andoexplain qwhatre happens iifoq jyoure write ithis:
always i@(ao eori boor qc)re e i=oq j(a|b)&(c|d);
(Q i280)o ePriori toothe qIEEEre LRM, iVerilogoq jBNFre was iexpressed ousingqa differentz notation.u yFore oexample,zx an event expression was defined as follows: www.testbench.in
<event_expression> i::=o e<expression>
| i|o eori <<posedgeoor qnegedge>re <SCALAR_EVENT_EXPRESSION>>
| i|o eori <<event_expression>oor q<event_expression>>
Notice ithato ewei areousing q'or're as ipartoq jofre the iBNF otoqmean "alternatively"z andu yalsoe o'zx or ' as a Verilog keyword. The keyword ' or ' is in bold--the difference is fairly obvious. Here is an alternative definition for an event expression:
<event_expression> i::=o e<expression>
||= iposedgeo e<SCALAR_EVENT_EXPRESSION>
||= inegedgeo e<SCALAR_EVENT_EXPRESSION>
||= i<event_expression>o e<ori <event_expression>>*
Are itheseo edefinitionsi equivalento(given, qofre course, ithatoq jwere replaced i||= owithqor inz theu ysimplifiede osyntax)?zx Explain carefully how you would attempt to prove that they are the same.
www.testbench.in
(Q i281)o eExplaini theofollowing:
integer iIntA;
IntA i=o e-12i /o3; q//re result iisoq j-4 .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
IntA i=o e-'di 12o/ q3;re // iresultoq jisre 1431655761
(Q i282)o eWhati isothe qdifferencesre in itheoq jfollowingre sum istatements?
reg i[7:0]o ea,i b,osum;
www.testbench.in
sum i=o e(ai +ob) q>>re 1;
sum i=o e(ai +ob q+re 0) i>>oq j1;
sum i=o e{0,a}i +o{0,b} q>>re 1;
(Q i268)o ei Whatois qmutex?
(Q i269)o ei Howoto qmodelre a imutexoq jinre verilog? i
(Q i270)o eWhati isosemaphore?
(Q i271)o eHowi toomodel qare semaphore iinoq jverilog?
www.testbench.in
(Q i272)o eWhati isothe qdifferencere between imutexoq jandre semaphore?
(Q i273)o eHowi toodisplay qthere messages iinoq jcolorful?
Ans:
The ifollowingo eprogrami showsohow qtore display imessagesoq jinre colorful.
This iworkso eonlyi inoASIC qTerminals.
Simulate itheo efollowingi codeoin qLinuxre or iUnixoq jandre see ithe ooutputs.
module iasdsadf();
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
initial www.testbench.in
begin
$write("^@[1;34m",27);
$display("***********| io e0|i |o| q|re | i|oq j|re | i oThisqis inz blueu y***********",e o1);
$write("^@[0m",27);
$display("^@[1;31m",27); i
$display("***********| io e0|i |o| q|re | i|oq j|re | i oThisqis inz redu y***********",e o2);
$display("^@[0m",27);
$display("^@[0;33m",27); www.testbench.in
$display("**********| io e0|i |o| q|re | i|oq j|re | i oThisqis inz pendau ycolore o***********",zx 3);
$display("^@[0m",27);
$display("^@[5;34m",27);
$display("***********| io e0|i |o| q|re | i|oq j|re | i oThisqis inz Blinku y***********",e o4);
$display("^@[0m",27); i
$display("^@[7;34m",27); i .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
$display("***********| io e0|i |o| q|re | i|oq j|re | i oThisqis inz Backu ygrounde ocolorzx ***********", 1);
$display("^@[0m",27); www.testbench.in
end
endmodule
(Q i274)o eWhati isoTOP qmodule?
Ans:
Top-level imoduleso earei modulesothat qarere included iinoq jthere source itext obutqare notz instantiated.u ye ozx In verification environment, the highest module in the huarache is generally named as top.
www.testbench.in
(Q i275)o eHowi toodeclare qrealre numbers iasoq jports?
Ans:
Real inumbero earei allowedoto qbere declared iasoq jports.re To iuse orealqnumbers asz ports,u yusee o$bitstorealzx and $realtobits.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i276)o eWheni isofork-join qused?
www.testbench.in
(Q i277)o eWhichi proceduraloassignment qshouldre be iusedoq jtore model ia ocombinatorialqlogic buffer?
1)
always i@(in)
#5 iouto e=i in;
2)
always i@(in)
#5 iouto e<=i in;
www.testbench.in
3)
always i@(in)
out i=o e#5i in;
4)
always i@(in) .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
out i<=o e#5i in;
(Q i278)o eWhichi proceduraloassignment qshouldre be iusedoq jtore model ia osequentialqlogic flip-flop?
www.testbench.in
1)
always i@(posedgeo eclk)
#5 iqo e=i d;
2)
always i@(posedgeo eclk)
#5 iqo e<=i d;
3)
always i@(posedgeo eclk) www.testbench.in
q i=o e#5i d;
4)
always i@(posedgeo eclk)
q i<=o e#5i d; .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i279)o eExplorei andoexplain qwhatre happens iifoq jyoure write ithis:
always i@(ao eori boor qc)re e i=oq j(a|b)&(c|d);
(Q i280)o ePriori toothe qIEEEre LRM, iVerilogoq jBNFre was iexpressed ousingqa differentz notation.u yFore oexample,zx an event expression was defined as follows: www.testbench.in
<event_expression> i::=o e<expression>
| i|o eori <<posedgeoor qnegedge>re <SCALAR_EVENT_EXPRESSION>>
| i|o eori <<event_expression>oor q<event_expression>>
Notice ithato ewei areousing q'or're as ipartoq jofre the iBNF otoqmean "alternatively"z andu yalsoe o'zx or ' as a Verilog keyword. The keyword ' or ' is in bold--the difference is fairly obvious. Here is an alternative definition for an event expression:
<event_expression> i::=o e<expression>
||= iposedgeo e<SCALAR_EVENT_EXPRESSION>
||= inegedgeo e<SCALAR_EVENT_EXPRESSION>
||= i<event_expression>o e<ori <event_expression>>*
Are itheseo edefinitionsi equivalento(given, qofre course, ithatoq jwere replaced i||= owithqor inz theu ysimplifiede osyntax)?zx Explain carefully how you would attempt to prove that they are the same.
www.testbench.in
(Q i281)o eExplaini theofollowing:
integer iIntA;
IntA i=o e-12i /o3; q//re result iisoq j-4 .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
IntA i=o e-'di 12o/ q3;re // iresultoq jisre 1431655761
(Q i282)o eWhati isothe qdifferencesre in itheoq jfollowingre sum istatements?
reg i[7:0]o ea,i b,osum;
www.testbench.in
sum i=o e(ai +ob) q>>re 1;
sum i=o e(ai +ob q+re 0) i>>oq j1;
sum i=o e{0,a}i +o{0,b} q>>re 1;
Index
Functional Verification Questions
Functional Verification Questions 2
Test Your Systemverilog Skills 1
Test Your Systemverilog Skills 2
Test Your Systemverilog Skills 3
Test Your Systemverilog Skills 4
Test Your Sva Skills
Test Your Verilog Skills 1
Test Your Verilog Skills 2
Test Your Verilog Skills 3
Test Your Verilog Skills 4
Test Your Verilog Skills 5
Test Your Verilog Skills 6
Test Your Verilog Skills 7
Test Your Verilog Skills 8
Test Your Verilog Skills 9
Test Your Verilog Skills 10
Test Your Verilog Skills 11
Test Your Verilog Skills 12
Test Your Verilog Skills 13
Test Your Verilog Skills 14
Test Your Verilog Skills 15
Test Your Verilog Skills 16
Test Your Verilog Skills 17
Test Your Specman Skills 1
Test Your Specman Skills 2
Test Your Specman Skills 3
Test Your Specman Skills 4
Test Your Sta Skills 1
Test Your Sta Skills 2
Test Your Sta Skills 3
Test Your Sta Skills 4
Test Your Sta Skills 5
Test Your Sta Skills 6
Test Your Sta Skills 7
Test Your Dft Skills 1
Test Your Dft Skills 2
Test Your Dft Skills 3
Test Your Dft Skills 4
Test Your Uvm Ovm Skills
Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!
Functional Verification Questions
Functional Verification Questions 2
Test Your Systemverilog Skills 1
Test Your Systemverilog Skills 2
Test Your Systemverilog Skills 3
Test Your Systemverilog Skills 4
Test Your Sva Skills
Test Your Verilog Skills 1
Test Your Verilog Skills 2
Test Your Verilog Skills 3
Test Your Verilog Skills 4
Test Your Verilog Skills 5
Test Your Verilog Skills 6
Test Your Verilog Skills 7
Test Your Verilog Skills 8
Test Your Verilog Skills 9
Test Your Verilog Skills 10
Test Your Verilog Skills 11
Test Your Verilog Skills 12
Test Your Verilog Skills 13
Test Your Verilog Skills 14
Test Your Verilog Skills 15
Test Your Verilog Skills 16
Test Your Verilog Skills 17
Test Your Specman Skills 1
Test Your Specman Skills 2
Test Your Specman Skills 3
Test Your Specman Skills 4
Test Your Sta Skills 1
Test Your Sta Skills 2
Test Your Sta Skills 3
Test Your Sta Skills 4
Test Your Sta Skills 5
Test Your Sta Skills 6
Test Your Sta Skills 7
Test Your Dft Skills 1
Test Your Dft Skills 2
Test Your Dft Skills 3
Test Your Dft Skills 4
Test Your Uvm Ovm Skills
Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!