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Specman E
Interview Questions
TEST YOUR VERILOG SKILLS 7
(Q
i
134)
o
e
can
i
I
o
use
q
a
r
e
Verilog
i
function
o
q
j
to
r
e
define
i
the
o
width
q
of a
z
multi-bit
u
y
port,
e
o
wire,
z
x
or reg type?
(Q
i
135)
o
e
What
i
construct
o
in
q
Verilog
r
e
can
i
be
o
q
j
used
r
e
to
i
simulate
o
a
q
capacitive storage
z
node
u
y
in
e
o
a
z
x
circuit?
Ans:
the
i
trireg
o
e
statement
i
is
o
used
q
to
r
e
simulate
i
a
o
q
j
wire
r
e
with
i
a
o
capacitive
q
hold value.
(Q
i
136)
o
e
Describe
i
the
o
basic
q
strength
r
e
system
i
in
o
q
j
Verilog.
Ans:
The
i
strength
o
e
system
i
has
o
8
q
values
r
e
0
i
through
o
q
j
7,
r
e
with
i
the
o
strongest
q
strength being
z
known
u
y
as
e
o
"supply"
z
x
and the weakest strength as high impedance.
www.testbench.in
(Q
i
137)
o
e
#define
i
cat(x,y)
o
x y
q
concatenates
r
e
x
i
to
o
q
j
y.
r
e
But
i
cat(cat(1,2),3)
o
does
q
not expand
z
but
u
y
gives
e
o
preprocessor
z
x
warning. Why?
Ans:
Because
i
parameterized
o
e
macros
i
are
o
not
q
recursive.
(Q
i
138)
o
e
What
i
are
o
the
q
types
r
e
of
i
strengths
o
q
j
that
r
e
can
i
be
o
specified
q
on a
z
net
u
y
??
Ans:
There
i
are
o
e
two
i
types
o
of
q
strengths
r
e
that
i
can
o
q
j
be
r
e
specified
i
in
o
a
q
net declaration.
z
They
u
y
are
e
o
as
z
x
follows:
charge
i
strength
o
e
shall
i
only
o
be
q
used
r
e
when
i
declaring
o
q
j
a
r
e
net
i
of
o
type
q
trireg
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
drive
i
strength
o
e
shall
i
only
o
be
q
used
r
e
when
i
placing
o
q
j
a
r
e
continuous
i
assignment
o
on
q
a net
z
in
u
y
the
e
o
same
z
x
statement that declares the net
www.testbench.in
(Q
i
139)
o
e
i
How
o
to
q
resolve
r
e
a
i
tristate
o
q
j
driver
r
e
in
i
Verilog
o
?
(Q
i
140)
o
e
i
WHAT
o
ARE
q
THE
r
e
TYPES
i
OF
o
q
j
CHARGE
r
e
STRENGTHS?
Ans:
SMALL,
i
MEDIUM,
o
e
LARGE
(Q
i
141)
o
e
How
i
to
o
model
q
power
r
e
supply
i
strengths
o
q
j
in
r
e
verilog?
Ans:
i
The
o
e
supply0
i
and
o
supply1
q
nets
r
e
may
i
be
o
q
j
used
r
e
to
i
model
o
the
q
power supplies
z
in
u
y
a
e
o
circuit.
z
x
These nets shall have supply strengths.
www.testbench.in
(Q
i
142)
o
e
How
i
to
o
modify
q
a
r
e
parameter
i
value?
Ans:
A
i
parameter
o
e
can
i
be
o
modified
q
with
r
e
the
i
defparam
o
q
j
statement
r
e
or
i
in
o
the
q
module instance
z
statement.
(Q
i
143)
o
e
What
i
is
o
localparam?
Ans:
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
local
i
parameter(s)
o
e
are
i
identical
o
to
q
parameters
r
e
except
i
that
o
q
j
they
r
e
can
i
not
o
directly
q
be modified
z
with
u
y
the
e
o
defparam
z
x
statement or by the ordered or named parameter value assignment.
www.testbench.in
(Q
i
144)
o
e
How
i
to
o
modify
q
r
e
a
i
localparam?
Ans:
Local
i
parameters
o
e
can
i
be
o
assigned
q
to
r
e
a
i
constant
o
q
j
expression
r
e
containing
i
a
o
parameter
q
which can
z
be
u
y
modified
e
o
with
z
x
the defparam statement or by the ordered or named parameter value assignment.
Parameter
i
o
e
WID
i
=
o
3
;
Localparam
i
WIDTH
o
e
=
i
2
*
WID
;
(Q
i
145)
o
e
WHAT
i
IS
o
specparam?
Ans:
www.testbench.in
specparam
i
declares
o
e
a
i
special
o
type
q
of
r
e
parameter
i
which
o
q
j
is
r
e
intended
i
only
o
for
q
providing timing
z
and
u
y
delay
e
o
values,
z
x
but can appear in any expression that is not assigned to a parameter and is not part of the range specification of a declaration. Unlike a module parameter, a specify parameter cannot be modified from within the language, but it may be modified through SDF annotation
(Q
i
146)
o
e
i
What
o
are
q
>>>
r
e
and
i
<<<
o
q
j
operators
r
e
?
(Q
i
147)
o
e
what
i
does
o
the
q
following
r
e
code
i
mean?
Reg
i
[
22
:
0
]
o
e
sig
;
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
always
@(|
sig
)
begin
www.testbench.in
......
end
(Q
i
148)
o
e
What
i
is
o
the
q
function
r
e
of
i
force
o
q
j
&
r
e
release?
Ans:
i
o
e
Force
i
and
o
release
q
statements
r
e
are
i
used
o
q
j
to
r
e
override
i
assignments
o
on
q
both registers
z
and
u
y
nets.
e
o
They
z
x
are typically used in the interactive debugging process, where certain registers or nets are forced to a value and the effect on other registers and nets is noted.
They
i
should
o
e
occur
i
only
o
in
q
simulation
r
e
block.
(Q
i
149)
o
e
What
i
is
o
the
q
purpose
r
e
of
i
declaring
o
q
j
tasks
r
e
or
i
functions
o
as
q
automatic?
Ans:
www.testbench.in
i
o
e
i
o
q
r
e
i
o
q
j
Declaration
r
e
of
i
tasks
o
and
q
functions as
z
Automatic
u
y
will
e
o
create
z
x
dynamic storage for each task or function call.
(Q
i
150)
o
e
What
i
is
o
Synthesis?
Ans:
Synthesis
i
is
o
e
the
i
stage
o
in
q
the
r
e
design
i
flow
o
q
j
which
r
e
is
i
concerned
o
with
q
translating your
z
Verilog
u
y
code
e
o
into
z
x
gates - and that's putting it very simply! First of all, the Verilog must be written in a particular way for the synthesis tool that you are using. Of course, a synthesis tool doesn't actually produce gates - it will output a netlist of the design that you have synthesized that represents the chip which can be fabricated through an ASIC or FPGA vendor.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Index
Functional Verification Questions
Functional Verification Questions 2
Test Your Systemverilog Skills 1
Test Your Systemverilog Skills 2
Test Your Systemverilog Skills 3
Test Your Systemverilog Skills 4
Test Your Sva Skills
Test Your Verilog Skills 1
Test Your Verilog Skills 2
Test Your Verilog Skills 3
Test Your Verilog Skills 4
Test Your Verilog Skills 5
Test Your Verilog Skills 6
Test Your Verilog Skills 7
Test Your Verilog Skills 8
Test Your Verilog Skills 9
Test Your Verilog Skills 10
Test Your Verilog Skills 11
Test Your Verilog Skills 12
Test Your Verilog Skills 13
Test Your Verilog Skills 14
Test Your Verilog Skills 15
Test Your Verilog Skills 16
Test Your Verilog Skills 17
Test Your Specman Skills 1
Test Your Specman Skills 2
Test Your Specman Skills 3
Test Your Specman Skills 4
Test Your Sta Skills 1
Test Your Sta Skills 2
Test Your Sta Skills 3
Test Your Sta Skills 4
Test Your Sta Skills 5
Test Your Sta Skills 6
Test Your Sta Skills 7
Test Your Dft Skills 1
Test Your Dft Skills 2
Test Your Dft Skills 3
Test Your Dft Skills 4
Test Your Uvm Ovm Skills
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