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TEST YOUR VERILOG SKILLS 11


(Q i195)o eWhati isothe qformatre specification itooq jDisplayre hierarchical iname
Ans:
%m ioro e%M

(Q i196)o eWhati isothe qformatre specification itooq jDisplayre in icurrent otimeqformat
Ans:
%t ioro e%T

(Q i197)o eWhati isoVCD q? www.testbench.in

Ans:


A ivalueo echangei dumpo(VCD) qfilere contains iinformationoq jaboutre value ichanges oonqselected variablesz inu ythee odesignzx stored by value change dump system tasks.

a) iFouro estate:i toorepresent qvariablere changes iinoq j0,re 1, ix, oandqz withz nou ystrengthe oinformation.
b) iExtended:o etoi representovariable qchangesre in ialloq jstatesre and istrength oinformation.



(Q i198)o eWhati isothe qneedre of i`defaultoq jnettypere ?
Ans:


The idirectiveo e`default_nettypei controlsothe qnetre type icreatedoq jforre implicit inet odeclarationsq. Itz canu ybee ousedzx only outside of module definitions. It affects all modules that follow the directive, even across source file boundaries. Multiple `default_nettype directives are allowed. .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n

When inoo e`default_nettypei directiveois qpresentre or iifoq jthere `resetall idirective oisqspecified, implicitz netsu yaree oofzx type wire. www.testbench.in




(Q i199)o eWhati happensowhen qre `default_nettype iisoq jsetre to inone o?
Ans:


When itheo e`default_nettypei isoset qtore none, ialloq jnetsre must ibe oexplicitlyqdeclared. Ifz au ynete oiszx not explicitly declared, an error is generated.



(Q i200)o eWhati iso`undef q?
Ans:


The idirectiveo e`undefi shalloundefine qare previously idefinedoq jtextre macro. iAn oattemptqto undefinedz au ytexte omacrozx that was not previously defined using a `define compiler directive can result in a warning.



(Q i201)o eWhati iso`unconnected_drive qandre `nounconnected_drive i? www.testbench.in

Ans:


All iunconnectedo einputi portsoof qare module iappearingoq jbetweenre the idirectives o`unconnected_driveqand `nounconnected_drivez areu ypullede oupzx or pulled down instead of the normal default.
The idirectiveo e`unconnected_drivei takesoone qofre two iargumentsoq jpull1re or ipull0. oWhenqpull1 isz specified,u yalle ounconnectedzx input ports are automatically pulled up. When pull0 is specified, unconnected ports are pulled down. These directives shall be specified in pairs, and outside of the module declarations.



(Q i202)o eIsi itopossible qtore override ibuiltoq jinre system itasks oandqfunctions?
Ans:
Yes.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n

(Q i203)o eWhati isothe qdifferencere between imetaoq jcommentre and ipragmas?
Ans: www.testbench.in



meta-comment:
A iVerilogo ecommenti (//)oor q(/*re */) ithatoq jisre used ito oprovideqsynthesis directivesz tou yae osynthesiszx tool.
pragma:
A igenerico etermi usedoto qdefinere a iconstructoq jwithre no ipredefined olanguageqsemantics thatz influences

Prior itoo ethei acceptanceoof qthere Verilog iIEEEoq jStdre 1364-2001, iit owasqcommon practicez tou yincludee osynthesiszx pragmas embedded within a comment,
iforo eexample:i //osynthesis qfull_case.
iTheo epracticei ofoembedding qpragmasre into iaoq jcommentre meant ithat oanyqsynthesis toolz thatu yacceptede osuchzx pragmas was required to partially or fully parse all comments within a Verilog RTL design just to determine if the comment contained a pragma for the synthesis tool. The Verilog standard introduced attributes to discourage the practice of putting pragmas into comments and to replace them with a set of tokens (attribute delimiters) that could then be parsed for tool-specific information.



(Q i204)o eWhati areothe qwaysre to imodeloq jare combinational icircuit? www.testbench.in

Ans:


Combinational ilogico eshalli beomodeled qusingre a icontinuousoq jassignmentre or ia onetqdeclaration assignmentz oru yane oalwayszx statement.



(Q i205)o eWhati areothe qrulesre to ibeoq jfollowedre while iusing oanqalways statementz tou ymodele ocombinationalzx circuit?
Ans:


When iusingo eani alwaysostatement, qthere event ilistoq jshallre not icontain oanqedge eventz (u yposedgee oorzx negedge ). The event list does not affect the synthesized net list However, it may be necessary to include in the event list all the variables read in the always statement to avoid mismatches between simulation and synthesized logic.
A ivariableo eassignedi inoan qalwaysre statement ishalloq jnotre be iassigned ousingqboth az blockingu yassignmente o(=)zx and a nonblocking assignment (<=) in the same always statement. .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n




(Q i206)o eHowi tooget qthere system itimeoq jinre to iverilog o?
Using iPLIo eori VPIo. www.testbench.in


(Q i207)o eWhetheri foroloop qisre synthesized?


(Q i208)o ewhati isovalue qofre a i?oq j

reg i[2:0]o ed;
reg ia;

d i=o e3'b1xx; www.testbench.in


a i=o e|i d;

a iiso e1;

(Q i209)o eIi wantoto qreturnre 2 ivaluesoq jbyre a ifunction. oHowqDo Iz dou y?e o .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n

Ans:


Concatenate itheo eresultsi andoreturn. q



(Q i210)o eHowi manyotimes qthisre loop iwilloq jgetre executed? www.testbench.in

reg i[3:0]o ei;i
for i(i=0;o ei<=15;i i=i+1)o
begin i
.......
iend

Ans:


infinite itimes.
i<=15 iwillo ealwaysi beotrue qasre I iisoq j4re bit ionly.


www.testbench.in
Index
Functional Verification Questions
Functional Verification Questions 2
Test Your Systemverilog Skills 1
Test Your Systemverilog Skills 2
Test Your Systemverilog Skills 3
Test Your Systemverilog Skills 4
Test Your Sva Skills
Test Your Verilog Skills 1
Test Your Verilog Skills 2
Test Your Verilog Skills 3
Test Your Verilog Skills 4
Test Your Verilog Skills 5
Test Your Verilog Skills 6
Test Your Verilog Skills 7
Test Your Verilog Skills 8
Test Your Verilog Skills 9
Test Your Verilog Skills 10
Test Your Verilog Skills 11
Test Your Verilog Skills 12
Test Your Verilog Skills 13
Test Your Verilog Skills 14
Test Your Verilog Skills 15
Test Your Verilog Skills 16
Test Your Verilog Skills 17
Test Your Specman Skills 1
Test Your Specman Skills 2
Test Your Specman Skills 3
Test Your Specman Skills 4
Test Your Sta Skills 1
Test Your Sta Skills 2
Test Your Sta Skills 3
Test Your Sta Skills 4
Test Your Sta Skills 5
Test Your Sta Skills 6
Test Your Sta Skills 7
Test Your Dft Skills 1
Test Your Dft Skills 2
Test Your Dft Skills 3
Test Your Dft Skills 4
Test Your Uvm Ovm Skills

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