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Specman E
Interview Questions
TEST YOUR VERILOG SKILLS 11
(Q
i
195)
o
e
What
i
is
o
the
q
format
r
e
specification
i
to
o
q
j
Display
r
e
hierarchical
i
name
Ans:
%m
i
or
o
e
%M
(Q
i
196)
o
e
What
i
is
o
the
q
format
r
e
specification
i
to
o
q
j
Display
r
e
in
i
current
o
time
q
format
Ans:
%t
i
or
o
e
%T
(Q
i
197)
o
e
What
i
is
o
VCD
q
?
www.testbench.in
Ans:
A
i
value
o
e
change
i
dump
o
(VCD)
q
file
r
e
contains
i
information
o
q
j
about
r
e
value
i
changes
o
on
q
selected variables
z
in
u
y
the
e
o
design
z
x
stored by value change dump system tasks.
a)
i
Four
o
e
state:
i
to
o
represent
q
variable
r
e
changes
i
in
o
q
j
0,
r
e
1,
i
x,
o
and
q
z with
z
no
u
y
strength
e
o
information.
b)
i
Extended:
o
e
to
i
represent
o
variable
q
changes
r
e
in
i
all
o
q
j
states
r
e
and
i
strength
o
information.
(Q
i
198)
o
e
What
i
is
o
the
q
need
r
e
of
i
`default
o
q
j
nettype
r
e
?
Ans:
The
i
directive
o
e
`default_nettype
i
controls
o
the
q
net
r
e
type
i
created
o
q
j
for
r
e
implicit
i
net
o
declarations
q
. It
z
can
u
y
be
e
o
used
z
x
only outside of module definitions. It affects all modules that follow the directive, even across source file boundaries. Multiple `default_nettype directives are allowed.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
When
i
no
o
e
`default_nettype
i
directive
o
is
q
present
r
e
or
i
if
o
q
j
the
r
e
`resetall
i
directive
o
is
q
specified, implicit
z
nets
u
y
are
e
o
of
z
x
type wire.
www.testbench.in
(Q
i
199)
o
e
What
i
happens
o
when
q
r
e
`default_nettype
i
is
o
q
j
set
r
e
to
i
none
o
?
Ans:
When
i
the
o
e
`default_nettype
i
is
o
set
q
to
r
e
none,
i
all
o
q
j
nets
r
e
must
i
be
o
explicitly
q
declared. If
z
a
u
y
net
e
o
is
z
x
not explicitly declared, an error is generated.
(Q
i
200)
o
e
What
i
is
o
`undef
q
?
Ans:
The
i
directive
o
e
`undef
i
shall
o
undefine
q
a
r
e
previously
i
defined
o
q
j
text
r
e
macro.
i
An
o
attempt
q
to undefined
z
a
u
y
text
e
o
macro
z
x
that was not previously defined using a `define compiler directive can result in a warning.
(Q
i
201)
o
e
What
i
is
o
`unconnected_drive
q
and
r
e
`nounconnected_drive
i
?
www.testbench.in
Ans:
All
i
unconnected
o
e
input
i
ports
o
of
q
a
r
e
module
i
appearing
o
q
j
between
r
e
the
i
directives
o
`unconnected_drive
q
and `nounconnected_drive
z
are
u
y
pulled
e
o
up
z
x
or pulled down instead of the normal default.
The
i
directive
o
e
`unconnected_drive
i
takes
o
one
q
of
r
e
two
i
arguments
o
q
j
pull1
r
e
or
i
pull0.
o
When
q
pull1 is
z
specified,
u
y
all
e
o
unconnected
z
x
input ports are automatically pulled up. When pull0 is specified, unconnected ports are pulled down. These directives shall be specified in pairs, and outside of the module declarations.
(Q
i
202)
o
e
Is
i
it
o
possible
q
to
r
e
override
i
built
o
q
j
in
r
e
system
i
tasks
o
and
q
functions?
Ans:
Yes.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q
i
203)
o
e
What
i
is
o
the
q
difference
r
e
between
i
meta
o
q
j
comment
r
e
and
i
pragmas?
Ans:
www.testbench.in
meta-comment:
A
i
Verilog
o
e
comment
i
(//)
o
or
q
(/*
r
e
*/)
i
that
o
q
j
is
r
e
used
i
to
o
provide
q
synthesis directives
z
to
u
y
a
e
o
synthesis
z
x
tool.
pragma:
A
i
generic
o
e
term
i
used
o
to
q
define
r
e
a
i
construct
o
q
j
with
r
e
no
i
predefined
o
language
q
semantics that
z
influences
Prior
i
to
o
e
the
i
acceptance
o
of
q
the
r
e
Verilog
i
IEEE
o
q
j
Std
r
e
1364-2001,
i
it
o
was
q
common practice
z
to
u
y
include
e
o
synthesis
z
x
pragmas embedded within a comment,
i
for
o
e
example:
i
//
o
synthesis
q
full_case.
i
The
o
e
practice
i
of
o
embedding
q
pragmas
r
e
into
i
a
o
q
j
comment
r
e
meant
i
that
o
any
q
synthesis tool
z
that
u
y
accepted
e
o
such
z
x
pragmas was required to partially or fully parse all comments within a Verilog RTL design just to determine if the comment contained a pragma for the synthesis tool. The Verilog standard introduced attributes to discourage the practice of putting pragmas into comments and to replace them with a set of tokens (attribute delimiters) that could then be parsed for tool-specific information.
(Q
i
204)
o
e
What
i
are
o
the
q
ways
r
e
to
i
model
o
q
j
a
r
e
combinational
i
circuit?
www.testbench.in
Ans:
Combinational
i
logic
o
e
shall
i
be
o
modeled
q
using
r
e
a
i
continuous
o
q
j
assignment
r
e
or
i
a
o
net
q
declaration assignment
z
or
u
y
an
e
o
always
z
x
statement.
(Q
i
205)
o
e
What
i
are
o
the
q
rules
r
e
to
i
be
o
q
j
followed
r
e
while
i
using
o
an
q
always statement
z
to
u
y
model
e
o
combinational
z
x
circuit?
Ans:
When
i
using
o
e
an
i
always
o
statement,
q
the
r
e
event
i
list
o
q
j
shall
r
e
not
i
contain
o
an
q
edge event
z
(
u
y
posedge
e
o
or
z
x
negedge ). The event list does not affect the synthesized net list However, it may be necessary to include in the event list all the variables read in the always statement to avoid mismatches between simulation and synthesized logic.
A
i
variable
o
e
assigned
i
in
o
an
q
always
r
e
statement
i
shall
o
q
j
not
r
e
be
i
assigned
o
using
q
both a
z
blocking
u
y
assignment
e
o
(=)
z
x
and a nonblocking assignment (<=) in the same always statement.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q
i
206)
o
e
How
i
to
o
get
q
the
r
e
system
i
time
o
q
j
in
r
e
to
i
verilog
o
?
Using
i
PLI
o
e
or
i
VPI
o
.
www.testbench.in
(Q
i
207)
o
e
Whether
i
for
o
loop
q
is
r
e
synthesized?
(Q
i
208)
o
e
what
i
is
o
value
q
of
r
e
a
i
?
o
q
j
reg
i
[2:0]
o
e
d;
reg
i
a;
d
i
=
o
e
3'b1xx;
www.testbench.in
a
i
=
o
e
|
i
d;
a
i
is
o
e
1;
(Q
i
209)
o
e
I
i
want
o
to
q
return
r
e
2
i
values
o
q
j
by
r
e
a
i
function.
o
How
q
Do I
z
do
u
y
?
e
o
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Ans:
Concatenate
i
the
o
e
results
i
and
o
return.
q
(Q
i
210)
o
e
How
i
many
o
times
q
this
r
e
loop
i
will
o
q
j
get
r
e
executed?
www.testbench.in
reg
i
[3:0]
o
e
i;
i
for
i
(i=0;
o
e
i<=15;
i
i=i+1)
o
begin
i
.......
i
end
Ans:
infinite
i
times.
i<=15
i
will
o
e
always
i
be
o
true
q
as
r
e
I
i
is
o
q
j
4
r
e
bit
i
only.
www.testbench.in
Index
Functional Verification Questions
Functional Verification Questions 2
Test Your Systemverilog Skills 1
Test Your Systemverilog Skills 2
Test Your Systemverilog Skills 3
Test Your Systemverilog Skills 4
Test Your Sva Skills
Test Your Verilog Skills 1
Test Your Verilog Skills 2
Test Your Verilog Skills 3
Test Your Verilog Skills 4
Test Your Verilog Skills 5
Test Your Verilog Skills 6
Test Your Verilog Skills 7
Test Your Verilog Skills 8
Test Your Verilog Skills 9
Test Your Verilog Skills 10
Test Your Verilog Skills 11
Test Your Verilog Skills 12
Test Your Verilog Skills 13
Test Your Verilog Skills 14
Test Your Verilog Skills 15
Test Your Verilog Skills 16
Test Your Verilog Skills 17
Test Your Specman Skills 1
Test Your Specman Skills 2
Test Your Specman Skills 3
Test Your Specman Skills 4
Test Your Sta Skills 1
Test Your Sta Skills 2
Test Your Sta Skills 3
Test Your Sta Skills 4
Test Your Sta Skills 5
Test Your Sta Skills 6
Test Your Sta Skills 7
Test Your Dft Skills 1
Test Your Dft Skills 2
Test Your Dft Skills 3
Test Your Dft Skills 4
Test Your Uvm Ovm Skills
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