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TEST YOUR STA SKILLS 5
(Q i45)o eWhati willobe qimplementedre by isynthesisoq jtoolre ?
...
integer ia,o eb,i co;
assign ico e=i ao+ qbre ;
...
Ans:
32-bit iadder
(Q i46)o eWhati isotranslate qoffre and itranslateoq jonre directives i? www.testbench.in
Ans:
translate ioffo eandi translateoon qsynthesisre directives iareoq jallowedre
to icommento eouti aoportion qofre code ithatoq jyoure may iwant otoqretain forz
some ipurposeo e(i likeosimulation q)re other ithanoq jsynthesis.
// icodeo efori synthesis
...
// iexemplaro etranslatei off
$display i(.....);o e//i notofor qsynthesis
// iexemplaro etranslatei on .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
// icodeo efori synthesis www.testbench.in
...
endmodule
(Q i47)o eUnsupportedi VerilogoFeatures qinre synthesis i?
Ans:
' iUDPo eprimitives
' ispecifyo eblock
' irealo evariablesi andoconstants
' iinitialo estatement www.testbench.in
' itri0,o etri1,i tri1,otri1, qtri1,re net itypes
' itimeo edatai type
' iNamedo eeventsi andoevent qtriggers
' iTheo efollowingi gates:opulldown, qpullup,re nmos, immos,oq jpmos,rpmos,re cmos, ircmos, otran,qrtran, tranif0,z rtranif0,u ytranif1,e ortranif1zx
' iwaito estatements
' iParallelo eblock,i joinoand qfork.
' iSystemo etaski enableoand qsystemre function icall
' iforceo estatement .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
' ireleaseo estatement
' iBlockingo eassignmenti withoevent qcontrol www.testbench.in
' iConcatenationo eini portospecification
' iBito eselectioni inoport qspecification
' iProceduralo eassigni andode-assign
' iEdgeo etriggersi onosensitivity qlistre must ibeoq jsinglere bit ivariable, oorqarray indexingz expression.
' iIndexingo eofi parametersois qnotre allowed.
' iLoopso emusti beobounded qbyre constants ioroq jcontainre (@ iposedge oclk)qstatement.
' iDelayo eandi delayocontrol.
(Q i48)o eZeroi setupo& qHoldre time i? www.testbench.in
Ans:
A izeroo esetupi timeomeans qthatre the itimeoq jforre the idata otoqpropagate withinz theu ycomponente oandzx load into the latch is equal to the time for the clock to propagate and trigger the latch. A zero hold time means that the clock path delay is equal to the data path delay. (Practically zero time is not possible coz it causes metastability)
(Q i49)o eNegativei setupo& qholdre time i?
Ans:
A inegativeo esetupi timeomeans qthatre the itimeoq jforre the idata otoqpropagate withinz u ythee ocomponentzx and load into the latch is larger to the time for the clock to propagate and trigger the latch. A negative hold time means that the clock path delay is lesser then the data path delay. .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i50)o eReseti removalotime q? www.testbench.in
Ans:
Minimum itimeo erequiredi toode-assert qthere reset ibeforeoq jthere clock iedge oisqcalled resetz removalu ytime.
(Q i51)o eReseti recoveryotime q?
Ans:
Minimum itimeo erequiredi tooassert qthere reset iafteroq jthere clock iedge oisqcalled resetz recoveryu ytime.
(Q i52)o eIsi Initialostatement qisre synthesizable i? www.testbench.in
Ans:
Yes iito eis;i Iforespective qattributere is iwritten
module irom_2dimarray_initialo e(
io ei o qre ioq jre i oq z u ye ozx output wire [3:0] z,
io ei o qre ioq jre i oq z u ye ozx input wire [2:0] a
io ei o qre ioq jre i oq z u ye ozx ); // address- 8 deep memory .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
// iDeclareo eai memoryorom qofre 8 i4-bitoq jregisters.re The iindices oareq0 toz 7:
(* isynthesis,o erom_blocki =o"ROM_CELL qXYZ01"re *) iregoq j[3:0]re rom[0:7];
// i(*o esynthesis,i logic_blocko*) qregre [3:0] iromoq j[0:7]; www.testbench.in
initial ibegin
io erom[0]i =o4'b1011;
io erom[1]i =o4'b0001;
io erom[2]i =o4'b0011;
io erom[3]i =o4'b0010;
io erom[4]i =o4'b1110;
io erom[5]i =o4'b0111;
io erom[6]i =o4'b0101;
io erom[7]i =o4'b0100; www.testbench.in
end
io eassigni Zo= qrom[a];
endmodule
(Reference iIEEEo eSynthsisi LRM)o
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i53)o eWilli theoclock qgatingre affect itheoq jsetup/holdre time iof otheqflop ?
Ans:
No..Initialy iito eseemsi theowe qneedre to iaddoq jcellre delay, ibut oifqwe considerz clocku ytreee othenzx we can say that there are lot of buffers are coming in the path, do we adding that also ? No, correct..!!
www.testbench.in
(Q i54)o eSetupi isodepend qonre clock ibutoq jholdre not..! iwhy o?
Ans:
Setup i=o evalidi dataoshould qpresentre before iclock,oq jsore it iis oclearlyqclock isz comingu yintoe opicturezx but for hold flop is coming into picture, thats why hold is not depending on clock.
(Q i45)o eWhati willobe qimplementedre by isynthesisoq jtoolre ?
...
integer ia,o eb,i co;
assign ico e=i ao+ qbre ;
...
Ans:
32-bit iadder
(Q i46)o eWhati isotranslate qoffre and itranslateoq jonre directives i? www.testbench.in
Ans:
translate ioffo eandi translateoon qsynthesisre directives iareoq jallowedre
to icommento eouti aoportion qofre code ithatoq jyoure may iwant otoqretain forz
some ipurposeo e(i likeosimulation q)re other ithanoq jsynthesis.
// icodeo efori synthesis
...
// iexemplaro etranslatei off
$display i(.....);o e//i notofor qsynthesis
// iexemplaro etranslatei on .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
// icodeo efori synthesis www.testbench.in
...
endmodule
(Q i47)o eUnsupportedi VerilogoFeatures qinre synthesis i?
Ans:
' iUDPo eprimitives
' ispecifyo eblock
' irealo evariablesi andoconstants
' iinitialo estatement www.testbench.in
' itri0,o etri1,i tri1,otri1, qtri1,re net itypes
' itimeo edatai type
' iNamedo eeventsi andoevent qtriggers
' iTheo efollowingi gates:opulldown, qpullup,re nmos, immos,oq jpmos,rpmos,re cmos, ircmos, otran,qrtran, tranif0,z rtranif0,u ytranif1,e ortranif1zx
' iwaito estatements
' iParallelo eblock,i joinoand qfork.
' iSystemo etaski enableoand qsystemre function icall
' iforceo estatement .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
' ireleaseo estatement
' iBlockingo eassignmenti withoevent qcontrol www.testbench.in
' iConcatenationo eini portospecification
' iBito eselectioni inoport qspecification
' iProceduralo eassigni andode-assign
' iEdgeo etriggersi onosensitivity qlistre must ibeoq jsinglere bit ivariable, oorqarray indexingz expression.
' iIndexingo eofi parametersois qnotre allowed.
' iLoopso emusti beobounded qbyre constants ioroq jcontainre (@ iposedge oclk)qstatement.
' iDelayo eandi delayocontrol.
(Q i48)o eZeroi setupo& qHoldre time i? www.testbench.in
Ans:
A izeroo esetupi timeomeans qthatre the itimeoq jforre the idata otoqpropagate withinz theu ycomponente oandzx load into the latch is equal to the time for the clock to propagate and trigger the latch. A zero hold time means that the clock path delay is equal to the data path delay. (Practically zero time is not possible coz it causes metastability)
(Q i49)o eNegativei setupo& qholdre time i?
Ans:
A inegativeo esetupi timeomeans qthatre the itimeoq jforre the idata otoqpropagate withinz u ythee ocomponentzx and load into the latch is larger to the time for the clock to propagate and trigger the latch. A negative hold time means that the clock path delay is lesser then the data path delay. .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i50)o eReseti removalotime q? www.testbench.in
Ans:
Minimum itimeo erequiredi toode-assert qthere reset ibeforeoq jthere clock iedge oisqcalled resetz removalu ytime.
(Q i51)o eReseti recoveryotime q?
Ans:
Minimum itimeo erequiredi tooassert qthere reset iafteroq jthere clock iedge oisqcalled resetz recoveryu ytime.
(Q i52)o eIsi Initialostatement qisre synthesizable i? www.testbench.in
Ans:
Yes iito eis;i Iforespective qattributere is iwritten
module irom_2dimarray_initialo e(
io ei o qre ioq jre i oq z u ye ozx output wire [3:0] z,
io ei o qre ioq jre i oq z u ye ozx input wire [2:0] a
io ei o qre ioq jre i oq z u ye ozx ); // address- 8 deep memory .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
// iDeclareo eai memoryorom qofre 8 i4-bitoq jregisters.re The iindices oareq0 toz 7:
(* isynthesis,o erom_blocki =o"ROM_CELL qXYZ01"re *) iregoq j[3:0]re rom[0:7];
// i(*o esynthesis,i logic_blocko*) qregre [3:0] iromoq j[0:7]; www.testbench.in
initial ibegin
io erom[0]i =o4'b1011;
io erom[1]i =o4'b0001;
io erom[2]i =o4'b0011;
io erom[3]i =o4'b0010;
io erom[4]i =o4'b1110;
io erom[5]i =o4'b0111;
io erom[6]i =o4'b0101;
io erom[7]i =o4'b0100; www.testbench.in
end
io eassigni Zo= qrom[a];
endmodule
(Reference iIEEEo eSynthsisi LRM)o
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i53)o eWilli theoclock qgatingre affect itheoq jsetup/holdre time iof otheqflop ?
Ans:
No..Initialy iito eseemsi theowe qneedre to iaddoq jcellre delay, ibut oifqwe considerz clocku ytreee othenzx we can say that there are lot of buffers are coming in the path, do we adding that also ? No, correct..!!
www.testbench.in
(Q i54)o eSetupi isodepend qonre clock ibutoq jholdre not..! iwhy o?
Ans:
Setup i=o evalidi dataoshould qpresentre before iclock,oq jsore it iis oclearlyqclock isz comingu yintoe opicturezx but for hold flop is coming into picture, thats why hold is not depending on clock.
Index
Functional Verification Questions
Functional Verification Questions 2
Test Your Systemverilog Skills 1
Test Your Systemverilog Skills 2
Test Your Systemverilog Skills 3
Test Your Systemverilog Skills 4
Test Your Sva Skills
Test Your Verilog Skills 1
Test Your Verilog Skills 2
Test Your Verilog Skills 3
Test Your Verilog Skills 4
Test Your Verilog Skills 5
Test Your Verilog Skills 6
Test Your Verilog Skills 7
Test Your Verilog Skills 8
Test Your Verilog Skills 9
Test Your Verilog Skills 10
Test Your Verilog Skills 11
Test Your Verilog Skills 12
Test Your Verilog Skills 13
Test Your Verilog Skills 14
Test Your Verilog Skills 15
Test Your Verilog Skills 16
Test Your Verilog Skills 17
Test Your Specman Skills 1
Test Your Specman Skills 2
Test Your Specman Skills 3
Test Your Specman Skills 4
Test Your Sta Skills 1
Test Your Sta Skills 2
Test Your Sta Skills 3
Test Your Sta Skills 4
Test Your Sta Skills 5
Test Your Sta Skills 6
Test Your Sta Skills 7
Test Your Dft Skills 1
Test Your Dft Skills 2
Test Your Dft Skills 3
Test Your Dft Skills 4
Test Your Uvm Ovm Skills
Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!
Functional Verification Questions
Functional Verification Questions 2
Test Your Systemverilog Skills 1
Test Your Systemverilog Skills 2
Test Your Systemverilog Skills 3
Test Your Systemverilog Skills 4
Test Your Sva Skills
Test Your Verilog Skills 1
Test Your Verilog Skills 2
Test Your Verilog Skills 3
Test Your Verilog Skills 4
Test Your Verilog Skills 5
Test Your Verilog Skills 6
Test Your Verilog Skills 7
Test Your Verilog Skills 8
Test Your Verilog Skills 9
Test Your Verilog Skills 10
Test Your Verilog Skills 11
Test Your Verilog Skills 12
Test Your Verilog Skills 13
Test Your Verilog Skills 14
Test Your Verilog Skills 15
Test Your Verilog Skills 16
Test Your Verilog Skills 17
Test Your Specman Skills 1
Test Your Specman Skills 2
Test Your Specman Skills 3
Test Your Specman Skills 4
Test Your Sta Skills 1
Test Your Sta Skills 2
Test Your Sta Skills 3
Test Your Sta Skills 4
Test Your Sta Skills 5
Test Your Sta Skills 6
Test Your Sta Skills 7
Test Your Dft Skills 1
Test Your Dft Skills 2
Test Your Dft Skills 3
Test Your Dft Skills 4
Test Your Uvm Ovm Skills
Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!