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Specman E
Interview Questions
FUNCTIONAL VERIFICATION QUESTIONS
(Q
i
1)Explain
o
e
how
i
to
o
inject
q
a
r
e
crc
i
error
o
q
j
in
r
e
a
i
packet
o
which
q
has just
z
data
u
y
and
e
o
crc
z
x
fields.
Ans:
Crc
i
error
o
e
injecttion
i
can
o
be
q
done
r
e
by
i
modifying
o
q
j
the
r
e
crc
i
value
o
only.
q
If
i
data
o
e
is
i
modified
o
to
q
inject
r
e
crc
i
error,
o
q
j
then
r
e
it
i
may
o
end
q
up in
z
a
u
y
situation
e
o
that
z
x
the new modified packet may have the same crc.
For
i
example
o
e
,
i
a
o
packet
q
of
r
e
length
i
5
o
q
j
bits
r
e
with
i
3
o
bits
q
of data
z
and
u
y
2
e
o
bits
z
x
of crc value.
Then
i
there
o
e
will
i
be
o
8
q
packets
r
e
of
i
different
o
q
j
data.
r
e
There
i
are
o
only
q
4 possible
z
crc
u
y
values.
e
o
So,
i
for
o
e
one
i
crc
o
value,
q
there
r
e
could
i
be
o
q
j
more
r
e
than
i
one
o
data
q
values which
z
are
u
y
correct.
www.testbench.in
If
i
you
o
e
modify
i
the
o
data,
q
then
r
e
the
i
new
o
q
j
data
r
e
may
i
have
o
the
q
same crc
z
value,
u
y
which
e
o
will
z
x
not be resulted as crc error.
For
i
one
o
e
data
i
field,
o
there
q
will
r
e
one
i
only
o
q
j
one
r
e
crc
i
value,
o
by
q
changing the
z
crc
u
y
value,
e
o
crc
z
x
error will be injected for sure.
(Q
i
2)
o
e
How
i
do
o
you
q
know
r
e
when
i
verification
o
q
j
completed?
Ans:
i
Verification
i
is
o
e
never
i
completed
o
as
q
per
r
e
me.
i
I
i
can
o
e
only
i
say
o
that
q
my
r
e
verification
i
task
o
q
j
is
r
e
completed
i
when
o
I
q
verified all
z
the
u
y
points
e
o
mentions
z
x
in test plan.
(Q
i
3)
o
e
How
i
to
o
detect
q
deadlock
r
e
conditions
i
in
o
q
j
FSMs
r
e
?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q
i
4)
o
e
How
i
to
o
avoid
q
race
r
e
condition
i
between
o
q
j
Testbench
r
e
and
i
DUT
o
?
www.testbench.in
Ans:
In
i
verilog
o
e
or
i
VHDL,
o
i
1)The
i
clock
o
e
which
i
is
o
given
q
to
r
e
DUT
i
and
o
q
j
Testbench
r
e
should
i
have
o
a
q
phase difference.
z
2)DUT
i
should
o
e
work
i
or
o
posedge
q
of
r
e
clock
i
and
o
q
j
testbench
r
e
should
i
work
o
on
q
negedge of
z
clock.
3)Testbench
i
output
o
e
and
i
DUT
o
output
q
pins
r
e
should
i
always
o
q
j
be
r
e
driven
i
using
o
non
q
blocking statements.
In
i
SV,
o
e
1)The
i
above
o
e
define
i
3
o
techniques.
2)Clocking
i
blocks.
www.testbench.in
3)Program
i
block.
(Q
i
5)
o
e
What
i
is
o
mutex?
Ans:
A
i
mutual
o
e
exclusion
i
or
o
MUTEX
q
r
e
essential
i
function
o
q
j
is
r
e
to
i
make
o
it
q
possible for
z
a
u
y
multiple
e
o
processes
z
x
to make use of a single resource.
When
i
a
o
e
single
i
resource
o
is
q
required
r
e
by
i
multiple
o
q
j
processes,
r
e
MUTEX
i
will
o
make
q
sure that
z
only
u
y
one
e
o
process
z
x
will be granted the access at a time.
For
i
example,
A
i
DUT
o
e
has
i
a
o
memory
q
to
r
e
store
i
the
o
q
j
configuration
r
e
registers.
i
To
o
access
q
the memory,
z
lets
u
y
say,
e
o
a
z
x
protocol is defined to read the memory of one location at a time.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Testbench
i
may
o
e
require
i
to
o
access
q
the
r
e
configuration/status/interrupt
i
registers
o
q
j
at
r
e
times
i
from
o
different
q
places. For
z
example,
u
y
a
e
o
monitor
z
x
is reading register location of status bit, while the testcase is reading a configuration register.
To
i
access
o
e
the
i
memory,
o
Testcase
q
and
r
e
monitor
i
will
o
q
j
send
r
e
the
i
address
o
of
q
the locations
z
and
u
y
read
e
o
command.
z
x
But the DUT can accept only one read request at a time.
www.testbench.in
By
i
using
o
e
MUTEX,
i
access
o
to
q
memory
r
e
interface
i
can
o
q
j
be
r
e
granted
i
once
o
at
q
a time,
z
so
u
y
the
e
o
read
z
x
operations by monitor and testcases will not collide.
In
i
SV,
o
e
to
i
create
o
a
q
MUTEX,
r
e
construct
i
a
o
q
j
semaphore
r
e
with
i
one
o
key.
A
i
key
o
e
is
i
given
o
q
to
r
e
either
i
monitor
o
q
j
or
r
e
testcase
i
to
o
read
q
operation based
z
on
u
y
who
e
o
comes
z
x
first. Once the key is returned, other waiting component can take the key and start its operation.
Some
i
times,
o
e
the
i
key
o
which
q
is
r
e
consumed
i
may
o
q
j
not
r
e
be
i
retuned
o
which
q
leads to
z
dead
u
y
lock
e
o
condition.
z
x
So if a key is not returned, then a timeout should happen and a error message should be triggered.
(Q
i
6)
o
e
What
i
is
o
semaphore?
Ans:
Conceptually,
i
a
o
e
semaphore
i
is
o
a
q
bucket.
r
e
When
i
a
o
q
j
semaphore
r
e
is
i
allocated,
o
a
q
bucket that
z
contains
u
y
a
e
o
fixed
z
x
number of keys is created. Processes using semaphores must first procure a key from the bucket before they can continue to execute. If a specific process requires a key, only a fixed number of occurrences of that process can be in progress simultaneously. All others must wait until a sufficient number of keys is returned to the bucket. Semaphores are typically used for mutual exclusion, access control to shared resources, and basic synchronization.
www.testbench.in
(Q
i
7)
o
e
What
i
is
o
the
q
need
r
e
of
i
regression?
Ans:
1)
i
Changes
o
e
in
i
the
o
RTL
q
(
r
e
development,
i
enhancement
o
q
j
or
r
e
bug
i
fix)
o
may
q
cause existing
z
functionality
u
y
to
e
o
break.
z
x
2)
i
To
o
e
create
i
new
o
scenarios
q
by
r
e
giving
i
different
o
q
j
seeds
r
e
to
i
randomization
o
engine.
q
(Q
i
8)
o
e
What
i
is
o
randomization?
Ans:
It
i
is
o
e
not
i
possible
o
to
q
list
r
e
out
i
every
o
q
j
possible
r
e
real
i
time
o
scenario
q
while verifying
z
DUT.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
If
i
we
o
e
try
i
to
o
list
q
out
r
e
the
i
scenarios,
o
q
j
then
r
e
we
i
may
o
miss
q
some of
z
them.
u
y
So,
e
o
using
z
x
randomization, based on the specification, scenarios are generated in a randomfashion.
For
i
example,
o
e
to
i
generate
o
a
q
packet
r
e
of
i
length
o
q
j
which
r
e
ranges
i
from
o
q
0 to
z
9,
u
y
in
e
o
verilog
z
x
{$random()} % 10 should be used.
With
i
this,
o
e
packets
i
of
o
length
q
are
r
e
generated
i
randomly.
o
q
j
www.testbench.in
(Q
i
9)
o
e
What
i
is
o
the
q
significance
r
e
of
i
seed
o
q
j
in
r
e
randomization?
Ans:
Seed
i
is
o
e
used
i
to
o
change
q
the
r
e
sequence
i
of
o
q
j
random
r
e
numbers
i
generated.
The
i
seed
o
e
initializes
i
o
the
q
random
r
e
number
i
generator.
o
q
j
All
i
the
o
e
random
i
numbers
o
which
q
are
r
e
generated
i
from
o
q
j
r
e
a
i
particular
o
seed
q
value can
z
be
u
y
recreated
e
o
z
x
by giving the same seed.
In
i
our
o
e
regressions,
i
stimulus
o
generation
q
is
r
e
done
i
randomly.
o
q
j
Running
r
e
the
i
complete
o
regression
q
will generate
z
same
u
y
random
e
o
numbers
z
x
if we use same seed.
So
i
our
o
e
regression
i
uses
o
the
q
time
r
e
of
i
test
o
q
j
case
r
e
simulation
i
started
o
as
q
the seed
z
to
u
y
random
e
o
number
z
x
generator, with this we are able to generate different stimulus for each regressions.
(Q
i
10)
o
e
What
i
is
o
the
q
difference
r
e
between
i
code
o
q
j
coverage
r
e
and
i
functional
o
coverage?
Ans:
www.testbench.in
Coverage
i
is
o
e
used
i
to
o
check
q
whether
r
e
the
i
Testbench
o
q
j
has
r
e
satisfactory
i
exercised
o
the
q
design or
z
not?
u
y
Code
i
coverage
o
e
will
i
give
o
information
q
about
r
e
how
i
many
o
q
j
lines
r
e
are
i
executed,
o
how
q
many times
z
expressions,
u
y
branches
e
o
executed.
z
x
This coverage is collected by the simulation tools. Users use this coverage to reach those corner cases which are not hit by the random testcases. Users have to write the directed testcases to reach the missing code coverage areas.
Functional
i
coverage
o
e
,
i
by
o
the
q
name
r
e
itself
i
,
o
q
j
is
r
e
related
i
to
o
the
q
functionality of
z
the
u
y
design
e
o
and
z
x
it is defined by the user. User will define the coverage points for the functions to be covered in DUT. This is completely under user control.
Both
i
of
o
e
them
i
have
o
equal
q
importance
r
e
in
i
the
o
q
j
verification.
r
e
100
i
o
0.000000unctional
q
coverage does
z
not
u
y
mean
e
o
that
z
x
the DUT is completely exercised and vice-versa. Verification engineers will consider both coverages to measure the verification progress.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q
i
11)
o
e
If
i
Code
o
Coverage
q
is
r
e
100%
i
and
o
q
j
functional
r
e
coverage
i
is
o
not,
q
what does
z
it
u
y
mean
e
o
?
Ans:
The
i
reason
o
e
could
i
be
o
any
q
one
r
e
of
i
the
o
q
j
following.
www.testbench.in
1)User
i
didnot
o
e
exercise
i
all
o
the
q
scenarios.
r
e
User
i
need
o
q
j
to
r
e
write
i
testcases
o
to
q
fill the
z
functional
u
y
coverage
e
o
holes.
2)There
i
could
o
e
be
i
a
o
bug
q
in
r
e
the
i
functional
o
q
j
coverage
r
e
block
i
which
o
is
q
not recording
z
the
u
y
executed
e
o
scenario.
z
x
User need to debug to find and fix the issue.
(Q
i
12)
o
e
If
i
Functional
o
coverage
q
is
r
e
100%
i
and
o
q
j
code
r
e
coverage
i
is
o
not,
q
then what
z
does
u
y
it
e
o
mean?
Ans:
1)
i
If
o
e
there
i
is
o
a
q
bug
r
e
in
i
test
o
q
j
environment,
r
e
due
i
to
o
this
q
test may
z
false
u
y
Pass.
e
o
The
z
x
functional coverage will hit due to this false pass but some of the dut code may not get exercised.
2)
i
If
o
e
the
i
dut
o
is
q
a
r
e
legacy
i
code
o
q
j
r
e
or
i
IP,
o
it
q
may have
z
some
u
y
use
e
o
less
z
x
blocks to support extra functionality. Due to this code coverage will not be 100% achieved.
3)
i
In
o
e
my
i
first
o
company,
q
r
e
there
i
was
o
q
j
some
r
e
use
i
less
o
logic
q
which did
z
not
u
y
get
e
o
exercised.
z
x
When I approached the RTL designer, he said that fixing this use less code will break the whole design. So he did not fix it. In this situation , functional coverage is 100%, but not the code coverage.
4)My
i
friends
o
e
experience,
i
once
o
RTL
q
designer
r
e
added
i
a
o
q
j
code
r
e
for
i
a
o
new
q
feature.
z
Because
u
y
of
e
o
miss
z
x
communication, my friend didnt know that RTL designer added this new functionality.
When
i
my
o
e
friend
i
did
o
the
q
code
r
e
coverage,
i
he
o
q
j
found
r
e
some
i
unexercised
o
logic
q
which he
z
didnt
u
y
understood
e
o
and
z
x
approached RTL designer. Then they figured out that because of miscommunication, they found a feature in the spec which was implemented, but not verified.
www.testbench.in
I
i
dont
o
e
think
i
,
o
point
q
2)
r
e
can
i
be
o
q
j
avoided.
r
e
Point
i
1),
o
3)
q
and 4)
z
can
u
y
be
e
o
solved.
z
x
(Q
i
13)
o
e
What
i
is
o
the
q
difference
r
e
between
i
passive
o
q
j
monitor
r
e
and
i
active
o
monitor.
Ans:
Monitor
i
reports
o
e
the
i
protocol
o
violation
q
and
r
e
identifies
i
all
o
q
j
the
r
e
transactions.
i
Monitors
o
are
q
two types,
z
Passive
u
y
and
e
o
active.
z
x
Passive monitors do not drive any signals, all the signals are inputs. Active monitors can drive the DUT signals. Sometimes this is also refered as receiver. Monitor converts the state of the design and its outputs to a transaction abstraction level so it can be stored in a 'score-boards' database to be checked later on. Monitor converts the pin level activities in to high level.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q
i
14)
o
e
In
i
simulation
o
environment,
q
under
r
e
what
i
condition
o
q
j
the
r
e
simulation
i
should
o
end?
Ans:
1)
i
Packet
o
e
count
i
match.
2)
i
Error
3)
i
Error
o
e
count
www.testbench.in
4)
i
Interface
o
e
idle
i
count
5)
i
Global
o
e
timeout
(Q
i
15)
o
e
What
i
is
o
scoreboard?
Ans:
The
i
term
o
e
SCOREBOARD
i
is
o
not
q
well-defined
r
e
in
i
the
o
q
j
industry.
r
e
It
i
sometimes
o
refers
q
to the
z
storage
u
y
data
e
o
structure
z
x
only, sometimes it includes the transfer function as well, and sometimes it includes the comparison function. In vmm methodology, the term scoreboard is used to refer to the entire dynamic response-checking structure.
(Q
i
16)
o
e
How
i
the
o
test
q
cases
r
e
are
i
included
o
q
j
in
r
e
to
i
simulation
o
environment?
Ans:
There
i
are
o
e
multiple
i
ways
o
to
q
do
r
e
this.
i
Two
i
very
o
e
simple
i
styles
o
are
q
discussed
r
e
in
i
below
o
q
j
link.
Click on the below link
http://www.testbench.in/TB_29_HANDLING_TESTCASE_FILES.html
www.testbench.in
(Q
i
17)
o
e
What
i
are
o
the
q
different
r
e
ways
i
testcase
o
q
j
are
r
e
included
i
for
o
simulations
q
?
Ans:
1)Compile
i
once,
o
e
simulate
i
multiple
o
times
q
with
r
e
different
i
testcases:
o
q
j
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Compile
i
Testbench
o
e
+
i
All
o
testcases
q
at
r
e
once
i
and
o
q
j
during
r
e
the
i
simulation,
o
using
q
the $plusargs,
z
select
u
y
the
e
o
logic
z
x
of a particular testcase and execute it.
This
i
style
o
e
is
i
sued
o
in
q
OVM
r
e
and
i
UVM.
o
q
j
This
i
style
o
e
should
i
make
o
sure
q
that,
r
e
when
i
the
o
q
j
test
r
e
is
i
executed
o
from
q
command line,
z
u
y
only
e
o
Testbench
z
x
+ required testcase should be compiled. Other wise, compiling all the testcases will consume huge time.
In
i
regression,
o
e
Compiling
i
all
o
the
q
testcases
r
e
+
i
testbenchs
o
q
j
at
r
e
once
i
will
o
save
q
time.
2)Separate
i
compilation:
www.testbench.in
i
Compile
o
e
the
i
testbench
o
once.
q
r
e
To
i
run
o
q
j
a
r
e
testcase,
i
compile
o
the
q
testcase ,
z
link
u
y
the
e
o
testcase
z
x
to testbench compiled code and simulate.
3)Compile
i
once,
o
e
simulate
i
once:
o
i
All
o
e
testcases
i
with
o
similar
q
configuration
r
e
setting
i
and
o
q
j
testbench
r
e
are
i
compiled
o
once
q
and simulated
z
in
u
y
one
e
o
single
z
x
run. After executing each testcase logic, HARD reset should be applied to DUT and BFMs, so that the simulation looks as if it started fresh for the next testcase code.
This
i
style
o
e
is
i
used
o
in
q
VMM
r
e
1.2.
i
o
q
j
This
r
e
style
i
saves
o
lot
q
of time
z
in
u
y
regressions.
4)Compile
i
once,
o
e
simulate
i
multiple
o
times
q
with
r
e
different
i
data:
o
q
j
In
i
some
o
e
verification
i
environments,
o
testcase
q
code
r
e
doesnt
i
need
o
q
j
to
r
e
be
i
compiles.
o
Testcase
q
file contains
z
some
u
y
data
e
o
which
z
x
is read by testbench to create different scenarios. Testcase file can be read using $fopen or $plusargs in Verilog.
There
i
could
o
e
be
i
many
o
more
q
ways
r
e
to
i
do
o
q
j
this.
r
e
www.testbench.in
If
i
you
o
e
know
i
something
o
which
q
is
r
e
not
i
mentioned
o
q
j
above
r
e
,
i
please
o
take
q
a minute
z
to
u
y
mail
e
o
it
z
x
to
gopi@testbench.in
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q
i
18)
o
e
Explain
i
how
o
messages
q
are
r
e
implemented
i
in
o
q
j
your
r
e
testbench?
Ans:
In
i
VMM/RVM/AVM/OVM/UVM/ERM/Truss&Teal
o
e
methodologies,
i
o
message
q
handling
r
e
logic
i
is
o
q
j
predefined.
r
e
Use
i
can
o
use
q
these predefined
z
message
u
y
services
e
o
and
z
x
print messages as required by testbench. If above methodology base classes are not used, then user can define his own message handling logic.
I
i
have
o
e
defined
i
a
o
simple
q
verilog
r
e
logic,
i
look
o
q
j
for
r
e
Message
i
Control
o
System
q
topic in
z
the
u
y
below
e
o
link
Click on the below link
http://www.testbench.in/TB_23_DEBUGGING.html
www.testbench.in
(Q
i
19)
o
e
Write
i
code
o
for
q
clock
r
e
generator?
Ans:
reg
i
clk;
initial
i
clk
o
e
=
i
0;
o
always
i
#10
o
e
clk
i
=
o
~clk;
q
(Q
i
20)
o
e
How
i
to
o
pass
q
a
r
e
value
i
to
o
q
j
testbench
r
e
from
i
command
o
line?
Ans:
Click on the below link
http://www.testbench.in/TB_22_COMPILATION_N_SIMULATION_SWITCHS.html
(Q
i
21)
o
e
What
i
is
o
test
q
plan
r
e
?
i
What
o
q
j
it
r
e
contains
i
?
Ans:
www.testbench.in
Click on the below link
http://www.testbench.in/TS_24_VERIFICATION_PLAN.html
(Q
i
22)
o
e
Explain
i
some
o
coding
q
guidelines
r
e
which
i
you
o
q
j
followed
r
e
in
i
your
o
environment?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q
i
23)
o
e
Explain
i
about
o
white
q
box/block
r
e
box
i
and
o
q
j
gray
r
e
box
i
testing.
Ans:
Click on the below link
http://www.testbench.in/TB_34_WHITE_GRAY_BLACK_BOX.html
Index
Functional Verification Questions
Functional Verification Questions 2
Test Your Systemverilog Skills 1
Test Your Systemverilog Skills 2
Test Your Systemverilog Skills 3
Test Your Systemverilog Skills 4
Test Your Sva Skills
Test Your Verilog Skills 1
Test Your Verilog Skills 2
Test Your Verilog Skills 3
Test Your Verilog Skills 4
Test Your Verilog Skills 5
Test Your Verilog Skills 6
Test Your Verilog Skills 7
Test Your Verilog Skills 8
Test Your Verilog Skills 9
Test Your Verilog Skills 10
Test Your Verilog Skills 11
Test Your Verilog Skills 12
Test Your Verilog Skills 13
Test Your Verilog Skills 14
Test Your Verilog Skills 15
Test Your Verilog Skills 16
Test Your Verilog Skills 17
Test Your Specman Skills 1
Test Your Specman Skills 2
Test Your Specman Skills 3
Test Your Specman Skills 4
Test Your Sta Skills 1
Test Your Sta Skills 2
Test Your Sta Skills 3
Test Your Sta Skills 4
Test Your Sta Skills 5
Test Your Sta Skills 6
Test Your Sta Skills 7
Test Your Dft Skills 1
Test Your Dft Skills 2
Test Your Dft Skills 3
Test Your Dft Skills 4
Test Your Uvm Ovm Skills
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