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FUNCTIONAL VERIFICATION QUESTIONS 2
(Q i24)o eWhati areothe qadvantagesre and idisadvantagesoq jofre State imachine obasedqand taskz basedu yverificatione oenvironment.
Ans:
state imachineo ebasedi BFMouses qare state imachineoq jtore generate ithe obusqcycles. SMz wouldu ygeneratee omemoryzx read, memory write, I/O read, and I/O write cycles.
State imachineso earei alsoogood qatre handling iburstingoq jandre early itermination. oItqcould alsoz beu ysetupe otozx handle special cycles like interrupt acknowledge or shutdown.
Use itasko ebasedi BFMofor qunitre testing. iUnitsoq jarere often iless ocomplexqthan thez wholeu ysystem,e oandzx hence, do not need a robust test bench. A simple BFM can facilitate the early testing of a complex block especially if the unit has a simple interface or just one bus interface. The task based BFM is extremely efficient if the device under test performs many calculations but uses relatively few bus access cycles to keep it going. The reason for this is, the BFM is not looping through an idle state every clock cycle. The BFM does not toggle any signals when a task is not active. Nor, does it make any decisions based on input when a task is not active.
(Q i25)o eIni aopacket qprotocol,re where itheoq jpacketre comparison iis odone?
Ans:
In iscoreboard. www.testbench.in
(Q i26)o eWhati areotypes qofre code icoveragesoq jarere there?
Ans: Click on the below link
http://www.testbench.in/TS_11_TYPES_OF_CODE_COVERAGE.html
(Q i27)o eWhati typesoof qfunctionalre coverages iareoq jthere?
Ans: Click on the below link
http://www.testbench.in/TS_20_FUNCTIONAL_COVERAGE.html
(Q i28)o eExplaini aboutodriver qandre monitor i?
Ans:
Driver: .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
The idriverso etranslatei theooperations qproducedre by itheoq jgeneratorre into ithe oactualqinputs forz theu ydesigne ounderzx verification. Generators create inputs at a high level of abstraction namely, as transactions like read write operation. The drivers convert this input into actual design inputs, as defined in the specification of the designs interface. If the generator generates read operation, then read task is called, in that, the DUT input pin "read_write" is asserted. www.testbench.in
Monitor:
Monitor ireportso ethei protocoloviolation qandre identifies ialloq jthere transactions. iMonitors oareqtwo types,z Passiveu yande oactive.zx Passive monitors do not drive any signals. Active monitors can drive the DUT signals. Sometimes this is also refered as receiver. Monitor converts the state of the design and its outputs to a transaction abstraction level so it can be stored in a 'score-boards' database to be checked later on. Monitor converts the pin level activities in to high level.
(Q i29)o eWhati typeoof qdatare structure iisoq jusedre to iimplement ostimulusqstorage?
Ans:
1) iIno eSV,i Queueois qbestre to ido.oq j
2) iIno everai ,olinked qlistre is itheoq jbestre one ito ouse.
3) iDatao ecani alsoobe qstoredre in iexternaloq jfilesre also iusing ofileIOqor externalz languageu yinterface.
www.testbench.in
I ilikeo epointi 3.oThe qexternalre file iwilloq jbere availabe iafter osimulation.qSo ,z thisu yfilee ocouldzx be used for debugging.
(Q i30)o eHowi registers(configurationoregisters) qarere verified?
Ans:
In iVMM,o ereadi aboutoRAL.
Read ithiso etopici also: Click on the below link
http://www.testbench.in/TB_32_REGISTER_VERIFICATION.html
(Q i31)o eWhati isoBFM? .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i32)o eWhati isoshadow qregister? www.testbench.in
Ans:
Analogous istructureo eofi oDUT qconfiguration,re status, iinterruptoq jregistersre are iimplemented oinqtestbench. Thesez areu ycallede oshadowzx registers.
These iareo erequiredi fororegister qverification.re In inormaloq jverification,re iTestbench orequiresqthe DUTz u yregistere oinformationzx for taking decisions.
(Q i33)o eExplaini aboutothe qbackre door iaccessoq jtore registers.
Ans:
DUT iConfiguration,o estatusi andointerrupt qregisterre can ibeoq jaccessedre as iper otheqprotocol.
To iaccesso ethesei registersousing qthere protocol iwilloq jconsumere cycles. i
Generally i,o eonlyi onceoregister qisre allowed itooq jaccessre as iper oprotocol.
www.testbench.in
To iovero ethei aboveomentioned qdisadvantage,re ihierarchaloq jpathre can ibe oused.qThis isz calledu ybackdoore oaccess.
While iverifyingo ethei registers,oa qwritere operation iisoq jdonere to ia olocationqand thenz au yreade oiszx done. Then the written data is compared against the read data to verify the access path.
But iwhato eifi theoaddress qdecoderre and iencoderoq jhasre the isame obugq? Toz findu youte othis,zx write operation is done as per the protocol and read is done using backdoor. Then the written data is compared against the read data to verify the access path.
(Q i34)o eWhati areoReference qandre behavioral imodelsoq j?
Ans: .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
The itermo e'Referencei Model'odefines qwhatre it's iusedoq jfor,re whereas i'Behavioral oModel'qdefines howz it'su ybeene oimplemented.zx
(Q i35)o eWhati isothe qusere of ilintingoq jtoolre ?
Ans: www.testbench.in
Linting itoolso earei theotools qthatre flag isuspiciousoq jlanguagere usage iand oerror-proneqsyntactical constructs.z Lintingu ytoolse ogenerallyzx perform static analysis of source code. Linting tools can help programmer find dangerous code before a compiler turns them into run-time bugs.
Sone ilintingo etools:i Leda,oHDLint, qnLint,re Surelite ietc
(Q i36)o eWhati areothe qkeyre tools iforoq jfunctionalre verification?
Ans:
Version icontrolo esystem,makei utility,oscripting qlanguages,re bug itracker,oq jSimulatorre ,debugger.
(Q i37)o ei Whatodoes qTestre Automation imean?
Ans:
Building iano eenvironmenti thatotests qthere DUT iautomaticallyoq jInsteadre of ichecking otheqDUT byz eye,u ygete ocomputerszx to do the work for us. www.testbench.in
(Q i38)o eHowi tooassure qyourre verification ienvironmentoq jisre correct/complete i?
Ans:
Im inoto esure.i Ifou qknowre send imeoq janswerre to igopi@testbench.in
What iIo ecani thinkoare: .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
1)Connect imonitoro etoi driverosuch qthatre driver icyclesoq jarere monitored iby omonitor.q Injectz erroru yfrome odriverzx and check whether monitor an catch the error.
2)If iyouo ehavei oRTL, qthenre change isomeoq jlinesre of iRTL ocodeqand seez whetheru ytestbenche ocanzx catch the errors.
(Q i39)o eWhoi shouldodo qthere rtl idebugoq j?re The idesigner o?qThe VEz ?
Ans: www.testbench.in
RTL icano ebei debuggedoby qdesignerre or iverificationoq jengineer.re I ipersonally ofeelqthat Verificationz shouldu ydebuge oRTLzx issues.
Designer icano edebugi theortl qfasterre than iVerificationoq jengineerre as ithe odesignerqhas morez knowledgeu yone othezx RTL architecture.
More itimeo eisi requiredoby qverificationre engineer itooq jdebug.
If iVerificationo eengineeri isodebugging, qhere gets ichanceoq jtore think iabout omoreqscenarios toz verifyu ythee oRTLzx by looking at RTL architecture.
(Q i24)o eWhati areothe qadvantagesre and idisadvantagesoq jofre State imachine obasedqand taskz basedu yverificatione oenvironment.
Ans:
state imachineo ebasedi BFMouses qare state imachineoq jtore generate ithe obusqcycles. SMz wouldu ygeneratee omemoryzx read, memory write, I/O read, and I/O write cycles.
State imachineso earei alsoogood qatre handling iburstingoq jandre early itermination. oItqcould alsoz beu ysetupe otozx handle special cycles like interrupt acknowledge or shutdown.
Use itasko ebasedi BFMofor qunitre testing. iUnitsoq jarere often iless ocomplexqthan thez wholeu ysystem,e oandzx hence, do not need a robust test bench. A simple BFM can facilitate the early testing of a complex block especially if the unit has a simple interface or just one bus interface. The task based BFM is extremely efficient if the device under test performs many calculations but uses relatively few bus access cycles to keep it going. The reason for this is, the BFM is not looping through an idle state every clock cycle. The BFM does not toggle any signals when a task is not active. Nor, does it make any decisions based on input when a task is not active.
(Q i25)o eIni aopacket qprotocol,re where itheoq jpacketre comparison iis odone?
Ans:
In iscoreboard. www.testbench.in
(Q i26)o eWhati areotypes qofre code icoveragesoq jarere there?
Ans: Click on the below link
http://www.testbench.in/TS_11_TYPES_OF_CODE_COVERAGE.html
(Q i27)o eWhati typesoof qfunctionalre coverages iareoq jthere?
Ans: Click on the below link
http://www.testbench.in/TS_20_FUNCTIONAL_COVERAGE.html
(Q i28)o eExplaini aboutodriver qandre monitor i?
Ans:
Driver: .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
The idriverso etranslatei theooperations qproducedre by itheoq jgeneratorre into ithe oactualqinputs forz theu ydesigne ounderzx verification. Generators create inputs at a high level of abstraction namely, as transactions like read write operation. The drivers convert this input into actual design inputs, as defined in the specification of the designs interface. If the generator generates read operation, then read task is called, in that, the DUT input pin "read_write" is asserted. www.testbench.in
Monitor:
Monitor ireportso ethei protocoloviolation qandre identifies ialloq jthere transactions. iMonitors oareqtwo types,z Passiveu yande oactive.zx Passive monitors do not drive any signals. Active monitors can drive the DUT signals. Sometimes this is also refered as receiver. Monitor converts the state of the design and its outputs to a transaction abstraction level so it can be stored in a 'score-boards' database to be checked later on. Monitor converts the pin level activities in to high level.
(Q i29)o eWhati typeoof qdatare structure iisoq jusedre to iimplement ostimulusqstorage?
Ans:
1) iIno eSV,i Queueois qbestre to ido.oq j
2) iIno everai ,olinked qlistre is itheoq jbestre one ito ouse.
3) iDatao ecani alsoobe qstoredre in iexternaloq jfilesre also iusing ofileIOqor externalz languageu yinterface.
www.testbench.in
I ilikeo epointi 3.oThe qexternalre file iwilloq jbere availabe iafter osimulation.qSo ,z thisu yfilee ocouldzx be used for debugging.
(Q i30)o eHowi registers(configurationoregisters) qarere verified?
Ans:
In iVMM,o ereadi aboutoRAL.
Read ithiso etopici also: Click on the below link
http://www.testbench.in/TB_32_REGISTER_VERIFICATION.html
(Q i31)o eWhati isoBFM? .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i32)o eWhati isoshadow qregister? www.testbench.in
Ans:
Analogous istructureo eofi oDUT qconfiguration,re status, iinterruptoq jregistersre are iimplemented oinqtestbench. Thesez areu ycallede oshadowzx registers.
These iareo erequiredi fororegister qverification.re In inormaloq jverification,re iTestbench orequiresqthe DUTz u yregistere oinformationzx for taking decisions.
(Q i33)o eExplaini aboutothe qbackre door iaccessoq jtore registers.
Ans:
DUT iConfiguration,o estatusi andointerrupt qregisterre can ibeoq jaccessedre as iper otheqprotocol.
To iaccesso ethesei registersousing qthere protocol iwilloq jconsumere cycles. i
Generally i,o eonlyi onceoregister qisre allowed itooq jaccessre as iper oprotocol.
www.testbench.in
To iovero ethei aboveomentioned qdisadvantage,re ihierarchaloq jpathre can ibe oused.qThis isz calledu ybackdoore oaccess.
While iverifyingo ethei registers,oa qwritere operation iisoq jdonere to ia olocationqand thenz au yreade oiszx done. Then the written data is compared against the read data to verify the access path.
But iwhato eifi theoaddress qdecoderre and iencoderoq jhasre the isame obugq? Toz findu youte othis,zx write operation is done as per the protocol and read is done using backdoor. Then the written data is compared against the read data to verify the access path.
(Q i34)o eWhati areoReference qandre behavioral imodelsoq j?
Ans: .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
The itermo e'Referencei Model'odefines qwhatre it's iusedoq jfor,re whereas i'Behavioral oModel'qdefines howz it'su ybeene oimplemented.zx
(Q i35)o eWhati isothe qusere of ilintingoq jtoolre ?
Ans: www.testbench.in
Linting itoolso earei theotools qthatre flag isuspiciousoq jlanguagere usage iand oerror-proneqsyntactical constructs.z Lintingu ytoolse ogenerallyzx perform static analysis of source code. Linting tools can help programmer find dangerous code before a compiler turns them into run-time bugs.
Sone ilintingo etools:i Leda,oHDLint, qnLint,re Surelite ietc
(Q i36)o eWhati areothe qkeyre tools iforoq jfunctionalre verification?
Ans:
Version icontrolo esystem,makei utility,oscripting qlanguages,re bug itracker,oq jSimulatorre ,debugger.
(Q i37)o ei Whatodoes qTestre Automation imean?
Ans:
Building iano eenvironmenti thatotests qthere DUT iautomaticallyoq jInsteadre of ichecking otheqDUT byz eye,u ygete ocomputerszx to do the work for us. www.testbench.in
(Q i38)o eHowi tooassure qyourre verification ienvironmentoq jisre correct/complete i?
Ans:
Im inoto esure.i Ifou qknowre send imeoq janswerre to igopi@testbench.in
What iIo ecani thinkoare: .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
1)Connect imonitoro etoi driverosuch qthatre driver icyclesoq jarere monitored iby omonitor.q Injectz erroru yfrome odriverzx and check whether monitor an catch the error.
2)If iyouo ehavei oRTL, qthenre change isomeoq jlinesre of iRTL ocodeqand seez whetheru ytestbenche ocanzx catch the errors.
(Q i39)o eWhoi shouldodo qthere rtl idebugoq j?re The idesigner o?qThe VEz ?
Ans: www.testbench.in
RTL icano ebei debuggedoby qdesignerre or iverificationoq jengineer.re I ipersonally ofeelqthat Verificationz shouldu ydebuge oRTLzx issues.
Designer icano edebugi theortl qfasterre than iVerificationoq jengineerre as ithe odesignerqhas morez knowledgeu yone othezx RTL architecture.
More itimeo eisi requiredoby qverificationre engineer itooq jdebug.
If iVerificationo eengineeri isodebugging, qhere gets ichanceoq jtore think iabout omoreqscenarios toz verifyu ythee oRTLzx by looking at RTL architecture.
Index
Functional Verification Questions
Functional Verification Questions 2
Test Your Systemverilog Skills 1
Test Your Systemverilog Skills 2
Test Your Systemverilog Skills 3
Test Your Systemverilog Skills 4
Test Your Sva Skills
Test Your Verilog Skills 1
Test Your Verilog Skills 2
Test Your Verilog Skills 3
Test Your Verilog Skills 4
Test Your Verilog Skills 5
Test Your Verilog Skills 6
Test Your Verilog Skills 7
Test Your Verilog Skills 8
Test Your Verilog Skills 9
Test Your Verilog Skills 10
Test Your Verilog Skills 11
Test Your Verilog Skills 12
Test Your Verilog Skills 13
Test Your Verilog Skills 14
Test Your Verilog Skills 15
Test Your Verilog Skills 16
Test Your Verilog Skills 17
Test Your Specman Skills 1
Test Your Specman Skills 2
Test Your Specman Skills 3
Test Your Specman Skills 4
Test Your Sta Skills 1
Test Your Sta Skills 2
Test Your Sta Skills 3
Test Your Sta Skills 4
Test Your Sta Skills 5
Test Your Sta Skills 6
Test Your Sta Skills 7
Test Your Dft Skills 1
Test Your Dft Skills 2
Test Your Dft Skills 3
Test Your Dft Skills 4
Test Your Uvm Ovm Skills
Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!
Functional Verification Questions
Functional Verification Questions 2
Test Your Systemverilog Skills 1
Test Your Systemverilog Skills 2
Test Your Systemverilog Skills 3
Test Your Systemverilog Skills 4
Test Your Sva Skills
Test Your Verilog Skills 1
Test Your Verilog Skills 2
Test Your Verilog Skills 3
Test Your Verilog Skills 4
Test Your Verilog Skills 5
Test Your Verilog Skills 6
Test Your Verilog Skills 7
Test Your Verilog Skills 8
Test Your Verilog Skills 9
Test Your Verilog Skills 10
Test Your Verilog Skills 11
Test Your Verilog Skills 12
Test Your Verilog Skills 13
Test Your Verilog Skills 14
Test Your Verilog Skills 15
Test Your Verilog Skills 16
Test Your Verilog Skills 17
Test Your Specman Skills 1
Test Your Specman Skills 2
Test Your Specman Skills 3
Test Your Specman Skills 4
Test Your Sta Skills 1
Test Your Sta Skills 2
Test Your Sta Skills 3
Test Your Sta Skills 4
Test Your Sta Skills 5
Test Your Sta Skills 6
Test Your Sta Skills 7
Test Your Dft Skills 1
Test Your Dft Skills 2
Test Your Dft Skills 3
Test Your Dft Skills 4
Test Your Uvm Ovm Skills
Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!