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TEST YOUR STA SKILLS 2
(Q i9)o eWhati dooyou qmeanre by inetoq jdelayre and icell odelayq?
Ans:
Time irequireo etoi chargeoor qdischargere all iparasiticoq jofre the inet ocalledqnetdelay andz timeu yinpute otransitionzx or slew rate of gate is called cell delay.
(Q i10)o eSetupi andoHold qtimere ?
Ans:
Valid idatao eshouldi beostable qbeforere the iclockoq jedgere and iafter otheqclock edgez isu ycallede osetupzx and hold time.
www.testbench.in
(Q i11)o eCriticali patho?
Ans:
The ipatho ewhichi hasoa qlargestre delay/longest ipathoq jisre called icritical opath.
(Q i12)o eSlacki ?
Ans:
Amount iofo etimingi marginoin qwhichre device imayoq jworkre properly ior omayqnot bez thatu ytiminge oanalysiszx is called slack.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
www.testbench.in
(Q i13)o ePositivei andoNegative qslackre ?
Ans:
The imargino eofi timeoin qwhichre design icanoq jworkre functionally icorrect oisqcalled positivez slacku yande ovicezx versa for negative slack.
(Q i14)o eSkewi ?
Ans:
Clock iarrivingo etimei toothe qflip-flopre is icalledoq jskew.
www.testbench.in
(Q i15)o eTypesi ofoskew q?
Ans:
local iskewo e-i timeodifference qofre arriving iclockoq jtore 1st iflop otoqleaf flopz fromu ythee oclockzx pin of ASIC is called local skew.
global iskewo e-i timeodifference qofre arriving iclockoq jfromre clock igenerator otoqthe z clocku ypine oiszx called global skew.
(Q i16)o ewhati doesoclock qskewre caused i?
Ans: .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Setup itimeo eviolation.
www.testbench.in
(Q i17)o ePropagationi delayo?
Ans:
Time irequireo etoi passodata qfromre the iregoq jisre called ipropagation odelay.
(Q i18)o eInputsi ofothe qsynthesisre tool i?
Ans:
RTL iDesingo efile,i Libraryofile qandre constrain iareoq jthere input iof otheqsynthesis tool.
www.testbench.in
(Q i9)o eWhati dooyou qmeanre by inetoq jdelayre and icell odelayq?
Ans:
Time irequireo etoi chargeoor qdischargere all iparasiticoq jofre the inet ocalledqnetdelay andz timeu yinpute otransitionzx or slew rate of gate is called cell delay.
(Q i10)o eSetupi andoHold qtimere ?
Ans:
Valid idatao eshouldi beostable qbeforere the iclockoq jedgere and iafter otheqclock edgez isu ycallede osetupzx and hold time.
www.testbench.in
(Q i11)o eCriticali patho?
Ans:
The ipatho ewhichi hasoa qlargestre delay/longest ipathoq jisre called icritical opath.
(Q i12)o eSlacki ?
Ans:
Amount iofo etimingi marginoin qwhichre device imayoq jworkre properly ior omayqnot bez thatu ytiminge oanalysiszx is called slack.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
www.testbench.in
(Q i13)o ePositivei andoNegative qslackre ?
Ans:
The imargino eofi timeoin qwhichre design icanoq jworkre functionally icorrect oisqcalled positivez slacku yande ovicezx versa for negative slack.
(Q i14)o eSkewi ?
Ans:
Clock iarrivingo etimei toothe qflip-flopre is icalledoq jskew.
www.testbench.in
(Q i15)o eTypesi ofoskew q?
Ans:
local iskewo e-i timeodifference qofre arriving iclockoq jtore 1st iflop otoqleaf flopz fromu ythee oclockzx pin of ASIC is called local skew.
global iskewo e-i timeodifference qofre arriving iclockoq jfromre clock igenerator otoqthe z clocku ypine oiszx called global skew.
(Q i16)o ewhati doesoclock qskewre caused i?
Ans: .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Setup itimeo eviolation.
www.testbench.in
(Q i17)o ePropagationi delayo?
Ans:
Time irequireo etoi passodata qfromre the iregoq jisre called ipropagation odelay.
(Q i18)o eInputsi ofothe qsynthesisre tool i?
Ans:
RTL iDesingo efile,i Libraryofile qandre constrain iareoq jthere input iof otheqsynthesis tool.
www.testbench.in
Index
Functional Verification Questions
Functional Verification Questions 2
Test Your Systemverilog Skills 1
Test Your Systemverilog Skills 2
Test Your Systemverilog Skills 3
Test Your Systemverilog Skills 4
Test Your Sva Skills
Test Your Verilog Skills 1
Test Your Verilog Skills 2
Test Your Verilog Skills 3
Test Your Verilog Skills 4
Test Your Verilog Skills 5
Test Your Verilog Skills 6
Test Your Verilog Skills 7
Test Your Verilog Skills 8
Test Your Verilog Skills 9
Test Your Verilog Skills 10
Test Your Verilog Skills 11
Test Your Verilog Skills 12
Test Your Verilog Skills 13
Test Your Verilog Skills 14
Test Your Verilog Skills 15
Test Your Verilog Skills 16
Test Your Verilog Skills 17
Test Your Specman Skills 1
Test Your Specman Skills 2
Test Your Specman Skills 3
Test Your Specman Skills 4
Test Your Sta Skills 1
Test Your Sta Skills 2
Test Your Sta Skills 3
Test Your Sta Skills 4
Test Your Sta Skills 5
Test Your Sta Skills 6
Test Your Sta Skills 7
Test Your Dft Skills 1
Test Your Dft Skills 2
Test Your Dft Skills 3
Test Your Dft Skills 4
Test Your Uvm Ovm Skills
Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!
Functional Verification Questions
Functional Verification Questions 2
Test Your Systemverilog Skills 1
Test Your Systemverilog Skills 2
Test Your Systemverilog Skills 3
Test Your Systemverilog Skills 4
Test Your Sva Skills
Test Your Verilog Skills 1
Test Your Verilog Skills 2
Test Your Verilog Skills 3
Test Your Verilog Skills 4
Test Your Verilog Skills 5
Test Your Verilog Skills 6
Test Your Verilog Skills 7
Test Your Verilog Skills 8
Test Your Verilog Skills 9
Test Your Verilog Skills 10
Test Your Verilog Skills 11
Test Your Verilog Skills 12
Test Your Verilog Skills 13
Test Your Verilog Skills 14
Test Your Verilog Skills 15
Test Your Verilog Skills 16
Test Your Verilog Skills 17
Test Your Specman Skills 1
Test Your Specman Skills 2
Test Your Specman Skills 3
Test Your Specman Skills 4
Test Your Sta Skills 1
Test Your Sta Skills 2
Test Your Sta Skills 3
Test Your Sta Skills 4
Test Your Sta Skills 5
Test Your Sta Skills 6
Test Your Sta Skills 7
Test Your Dft Skills 1
Test Your Dft Skills 2
Test Your Dft Skills 3
Test Your Dft Skills 4
Test Your Uvm Ovm Skills
Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!