|
HOME
|
ABOUT
|
ARTICLES
|
ACK
|
FEEDBACK
|
TOC
|
LINKS
|
BLOG
|
JOBS
|
Tutorials
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
TEST YOUR SVA SKILLS
(Q
i
191)
o
e
What
i
is
o
the
q
difference
r
e
between
i
$rose
o
q
j
and
r
e
posedge
i
?
(Q
i
192)
o
e
When
i
an
o
assert
q
property
r
e
or
i
assume
o
q
j
property
r
e
matches?
(Q
i
193)
o
e
i
Tell
o
on
q
Assertion
r
e
Severity
i
Levels?
(Q
i
194)
o
e
Explaing
i
about
o
SVA
q
Layers?
(Q
i
195)
o
e
When
i
a
o
cover
q
property
r
e
matches?
www.testbench.in
(Q
i
196)
o
e
Difference
i
b/w
o
Procedural
q
and
r
e
Concurrent
i
Assertions
o
q
j
?
(Q
i
197)
o
e
How
i
many
o
types
q
of
r
e
assertions?
i
Explain?
(Q
i
198)
o
e
Equivalent
i
construct
o
to
q
|->
r
e
1
i
?
o
q
j
Ans:
i
o
e
|=>
(Q
i
199)
o
e
What
i
is
o
Sequence?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
www.testbench.in
(Q
i
200)
o
e
What
i
is
o
the
q
difference
r
e
between
i
assume
o
q
j
and
r
e
assert
i
?
(Q
i
201)
o
e
How
i
to
o
check
q
for
r
e
only
i
one
o
q
j
success
r
e
in
i
assertions
o
?
q
(Q
i
202)
o
e
Write
i
an
o
assertion
q
for
r
e
Glitch
i
detection
o
q
j
.
(Q
i
203)
o
e
what
i
is
o
the
q
difference
r
e
between
i
expect
o
q
j
and
r
e
assert
i
statement?
o
i
"Write
o
e
the
i
SVA
o
assertion
q
code
r
e
for
i
the
o
q
j
following
r
e
description"
www.testbench.in
(Q
i
204)
o
e
As
i
long
o
as
q
sig_a
r
e
is
i
still
o
q
j
up,
r
e
sig_b
i
should
o
not
q
be asserted.
(Q
i
205)
o
e
The
i
signal
o
sig_a
q
is
r
e
a
i
pulse:
o
q
j
It
r
e
can
i
only
o
be
q
asserted for
z
one
u
y
cycle,
e
o
and
z
x
must be deasserted in the next cycle.
(Q
i
206)
o
e
sig_a
i
is
o
a
q
pulse,
r
e
unless
i
sig_b
o
q
j
is
r
e
asserted.
(Q
i
207)
o
e
sig_a
i
and
o
sig_b
q
can
r
e
only
i
be
o
q
j
asserted
r
e
together
i
for
o
one
q
cycle; in
z
the
u
y
next
e
o
cycle,
z
x
at least one of them must be deasserted.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q
i
208)
o
e
If
i
sig_a
o
is
q
asserted
r
e
for
i
the
o
q
j
first
r
e
time,
i
then
o
it
q
must have
z
been
u
y
preceded
e
o
by
z
x
a sig_b.
www.testbench.in
(Q
i
209)
o
e
sig_a
i
must
o
not
q
be
r
e
asserted
i
before
o
q
j
the
r
e
first
i
sig_b
o
(may
q
be asserted
z
on
u
y
the
e
o
same
z
x
cycle as sig_b).
(Q
i
210)
o
e
When
i
sig_a
o
is
q
asserted,
r
e
sig_b
i
must
o
q
j
be
r
e
asserted,
i
and
o
must
q
remain up
z
until
u
y
one
e
o
of
z
x
the signals sig_c or sig_d is asserted.
(Q
i
211)
o
e
After
i
one
o
of
q
the
r
e
signals
i
sig_a
o
q
j
is
r
e
asserted,
i
sig_b
o
must
q
be deasserted,
z
and
u
y
must
e
o
stay
z
x
down until the next sig_a.
(Q
i
212)
o
e
The
i
signals
o
sig_a
q
and
r
e
sig_b
i
may
o
q
j
only
r
e
be
i
asserted
o
if
q
sig_c is
z
asserted.
(Q
i
213)
o
e
There
i
exists
o
a
q
transaction
r
e
that
i
reaches
o
q
j
its
r
e
end
i
o
either
q
sig_a
z
u
y
or
e
o
sig_b.
www.testbench.in
(Q
i
214)
o
e
If
i
sig_a
o
is
q
received
r
e
while
i
sig_b
o
q
j
is
r
e
inactive,
i
then
o
on
q
the next
z
cycle
u
y
sig_c
e
o
must
z
x
be inactive, and sig_b must be asserted.
(Q
i
215)
o
e
sig_a
i
must
o
not
q
rise
r
e
before
i
the
o
q
j
first
r
e
sig_b.
(Q
i
216)
o
e
sig_a
i
must
o
not
q
be
r
e
asserted
i
together
o
q
j
with
r
e
sig_b
i
o
or
q
with sig_c.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q
i
217)
o
e
sig_a
i
must
o
not
q
be
r
e
asserted
i
between
o
q
j
an
r
e
sig_b
i
and
o
the
q
following sig_c
z
(from
u
y
one
e
o
cycle
z
x
after the sig_b until one cycle after the sig_c).
(Q
i
218)
o
e
sig_a
i
must
o
not
q
be
r
e
asserted
i
together
o
q
j
with
r
e
sig_b
i
or
o
with
q
sig_c.
www.testbench.in
(Q
i
219)
o
e
If
i
we
o
are
q
at
r
e
the
i
end
o
q
j
of
r
e
a
i
transaction
o
(sig_a
q
is down,
z
sig_b
u
y
is
e
o
up),
z
x
and sig_c is down, then sig_c must be asserted before the next time that sig_a is asserted.
(Q
i
220)
o
e
If
i
sig_a
o
is
q
down,
r
e
sig_b
i
may
o
q
j
only
r
e
rise
i
for
o
one
q
cycle before
z
the
u
y
next
e
o
time
z
x
that sig_a is asserted.
(Q
i
221)
o
e
sig_a
i
must
o
not
q
rise
r
e
if
i
we
o
q
j
have
r
e
seen
i
sig_b
o
and
q
havent seen
z
the
u
y
next
e
o
sig_c
z
x
yet (from the cycle after the sig_b until the cycle of the sig_c).
(Q
i
222)
o
e
The
i
auxiliary
o
signal
q
sig_a
r
e
indicates
i
that
o
q
j
we
r
e
have
i
seen
o
a
q
sig_b, and
z
havent
u
y
seen
e
o
a
z
x
sig_c since then. It rises one cycle after the sig_b, and falls one cycle after the sig_c.
(Q
i
223)
o
e
sig_a
i
may
o
be
q
asserted
r
e
only
i
while
o
q
j
sig_b
r
e
is
i
true,
o
i.e.,
q
we are
z
at
u
y
least
e
o
one
z
x
cycle after a sig_c and havent seen a sig_d since then (except perhaps in the current cycle)
www.testbench.in
(Q
i
224)
o
e
sig_a
i
may
o
be
q
asserted
r
e
only
i
during
o
q
j
the
r
e
time
i
frame
o
beginning
q
with sig_b
z
(inclusive)
u
y
and
e
o
continuing
z
x
until sig_c rises (inclusive).
(Q
i
225)
o
e
sig_a
i
must
o
not
q
rise
r
e
if
i
we
o
q
j
have
r
e
seen
i
sig_b
o
and
q
havent seen
z
the
u
y
next
e
o
sig_c
z
x
yet (from the cycle after the sig_b until the cycle before the sig_c).
(Q
i
226)
o
e
While
i
sig_a
o
is
q
down,
r
e
sig_b
i
may
o
q
j
rise
r
e
only
i
if
o
sig_c
q
is down.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q
i
227)
o
e
If
i
sig_a
o
is
q
asserted
r
e
with
i
sig_b
o
q
j
inactive,
r
e
and
i
sig_c
o
was
q
inactive in
z
the
u
y
previous
e
o
cycle
z
x
and remains inactive in the next cycle, then sig_a must be deasserted in the next cycle.
(Q
i
228)
o
e
If
i
there
o
are
q
are
r
e
two
i
occurences
o
q
j
of
r
e
sig_a
i
rising
o
with
q
STATE=active1, and
z
no
u
y
sig_b
e
o
occurs
z
x
between them, then within 3 cycles of the second rise of sig_a, START must occur.
www.testbench.in
(Q
i
229)
o
e
Show
i
a
o
sequence
q
with
r
e
3
i
transactions
o
q
j
(in
r
e
which
i
sig_a
o
is
q
asserted 3
z
times).
(Q
i
230)
o
e
If
i
the
o
state
q
machine
r
e
reaches
i
STATE=active1,
o
q
j
it
r
e
will
i
eventually
o
reach
q
STATE=active2.
(Q
i
231)
o
e
sig_a
i
is
o
eventually
q
asserted,
r
e
after
i
sig_b
o
q
j
has
r
e
fallen.
(Q
i
232)
o
e
sig_a
i
is
o
eventually
q
asserted
r
e
without
i
sig_b
o
q
j
indication,
r
e
after
i
sig_c
o
has
q
fallen.
(Q
i
233)
o
e
If
i
sig_a
o
is
q
active,
r
e
then
i
sig_b
o
q
j
was
r
e
active
i
3
o
cycles
q
ago.
www.testbench.in
(Q
i
234)
o
e
If
i
sig_a
o
is
q
active,
r
e
then
i
sig_b
o
q
j
was
r
e
active
i
somewhere
o
in
q
the past.
(Q
i
235)
o
e
If
i
there
o
is
q
a
r
e
sig_a,
i
followed
o
q
j
by
r
e
3
i
consecutive
o
sig_b,
q
then in
z
each
u
y
of
e
o
the
z
x
3 cycles the data written (DO) is equal to the data read (DI).
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q
i
236)
o
e
Always,
i
if
o
on
q
3
r
e
consecutive
i
sig_a,
o
q
j
sig_b
r
e
appears,
i
then
o
on
q
the next
z
sig_c
u
y
cycle,
e
o
sig_a
z
x
holds.
(Q
i
237)
o
e
Every
i
sig_a
o
must
q
eventually
r
e
be
i
acknowledged
o
q
j
by
r
e
sig_b,
i
unless
o
sig_c
q
appears
(Q
i
238)
o
e
sig_a
i
occurs
o
n
q
cycles
r
e
after
i
sig_b.
www.testbench.in
(Q
i
239)
o
e
sig_a
i
and
o
sig_b
q
are
r
e
environment
i
signals,
o
q
j
which
r
e
can
i
be
o
given
q
at any
z
time,
u
y
but
e
o
should
z
x
never be given together.
(Q
i
240)
o
e
If
i
sig_a
o
is
q
active,
r
e
it
i
must
o
q
j
be
r
e
deactivated
i
one
o
cycle
q
after sig_b
z
arrives.
u
y
Note
e
o
that
z
x
sig_a may already be active when sig_b is asserted.
Index
Functional Verification Questions
Functional Verification Questions 2
Test Your Systemverilog Skills 1
Test Your Systemverilog Skills 2
Test Your Systemverilog Skills 3
Test Your Systemverilog Skills 4
Test Your Sva Skills
Test Your Verilog Skills 1
Test Your Verilog Skills 2
Test Your Verilog Skills 3
Test Your Verilog Skills 4
Test Your Verilog Skills 5
Test Your Verilog Skills 6
Test Your Verilog Skills 7
Test Your Verilog Skills 8
Test Your Verilog Skills 9
Test Your Verilog Skills 10
Test Your Verilog Skills 11
Test Your Verilog Skills 12
Test Your Verilog Skills 13
Test Your Verilog Skills 14
Test Your Verilog Skills 15
Test Your Verilog Skills 16
Test Your Verilog Skills 17
Test Your Specman Skills 1
Test Your Specman Skills 2
Test Your Specman Skills 3
Test Your Specman Skills 4
Test Your Sta Skills 1
Test Your Sta Skills 2
Test Your Sta Skills 3
Test Your Sta Skills 4
Test Your Sta Skills 5
Test Your Sta Skills 6
Test Your Sta Skills 7
Test Your Dft Skills 1
Test Your Dft Skills 2
Test Your Dft Skills 3
Test Your Dft Skills 4
Test Your Uvm Ovm Skills
Report a Bug or Comment on This section
- Your input is what keeps Testbench.in improving with time!