(Q i191)o eWhati isothe qdifferencere between i$roseoq jandre posedge i?

(Q i192)o eWheni anoassert qpropertyre or iassumeoq jpropertyre matches?

(Q i193)o ei Telloon qAssertionre Severity iLevels?

(Q i194)o eExplaingi aboutoSVA qLayers?

(Q i195)o eWheni aocover qpropertyre matches? www.testbench.in

(Q i196)o eDifferencei b/woProcedural qandre Concurrent iAssertionsoq j?

(Q i197)o eHowi manyotypes qofre assertions? iExplain?

(Q i198)o eEquivalenti constructoto q|->re 1 i?oq j
Ans: io e|=>

(Q i199)o eWhati isoSequence? .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n


(Q i200)o eWhati isothe qdifferencere between iassumeoq jandre assert i?

(Q i201)o eHowi toocheck qforre only ioneoq jsuccessre in iassertions o?q

(Q i202)o eWritei anoassertion qforre Glitch idetectionoq j.

(Q i203)o ewhati isothe qdifferencere between iexpectoq jandre assert istatement? o

i"Writeo ethei SVAoassertion qcodere for itheoq jfollowingre description" www.testbench.in

(Q i204)o eAsi longoas qsig_are is istilloq jup,re sig_b ishould onotqbe asserted.

(Q i205)o eThei signalosig_a qisre a ipulse:oq jItre can ionly obeqasserted forz oneu ycycle,e oandzx must be deasserted in the next cycle.

(Q i206)o esig_ai isoa qpulse,re unless isig_boq jisre asserted.

(Q i207)o esig_ai andosig_b qcanre only ibeoq jassertedre together ifor ooneqcycle; inz theu ynexte ocycle,zx at least one of them must be deasserted. .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n

(Q i208)o eIfi sig_aois qassertedre for itheoq jfirstre time, ithen oitqmust havez beenu yprecedede obyzx a sig_b. www.testbench.in

(Q i209)o esig_ai mustonot qbere asserted ibeforeoq jthere first isig_b o(mayqbe assertedz onu ythee osamezx cycle as sig_b).

(Q i210)o eWheni sig_aois qasserted,re sig_b imustoq jbere asserted, iand omustqremain upz untilu yonee oofzx the signals sig_c or sig_d is asserted.

(Q i211)o eAfteri oneoof qthere signals isig_aoq jisre asserted, isig_b omustqbe deasserted,z andu ymuste ostayzx down until the next sig_a.

(Q i212)o eThei signalsosig_a qandre sig_b imayoq jonlyre be iasserted oifqsig_c isz asserted.

(Q i213)o eTherei existsoa qtransactionre that ireachesoq jitsre end i oeitherq sig_az u yore osig_b. www.testbench.in

(Q i214)o eIfi sig_aois qreceivedre while isig_boq jisre inactive, ithen oonqthe nextz cycleu ysig_ce omustzx be inactive, and sig_b must be asserted.

(Q i215)o esig_ai mustonot qrisere before itheoq jfirstre sig_b.

(Q i216)o esig_ai mustonot qbere asserted itogetheroq jwithre sig_b i oorqwith sig_c.

(Q i217)o esig_ai mustonot qbere asserted ibetweenoq janre sig_b iand otheqfollowing sig_cz (fromu yonee ocyclezx after the sig_b until one cycle after the sig_c).

(Q i218)o esig_ai mustonot qbere asserted itogetheroq jwithre sig_b ior owithqsig_c. www.testbench.in

(Q i219)o eIfi weoare qatre the iendoq jofre a itransaction o(sig_aqis down,z sig_bu yise oup),zx and sig_c is down, then sig_c must be asserted before the next time that sig_a is asserted.

(Q i220)o eIfi sig_aois qdown,re sig_b imayoq jonlyre rise ifor ooneqcycle beforez theu ynexte otimezx that sig_a is asserted.

(Q i221)o esig_ai mustonot qrisere if iweoq jhavere seen isig_b oandqhavent seenz theu ynexte osig_czx yet (from the cycle after the sig_b until the cycle of the sig_c).

(Q i222)o eThei auxiliaryosignal qsig_are indicates ithatoq jwere have iseen oaqsig_b, andz haventu yseene oazx sig_c since then. It rises one cycle after the sig_b, and falls one cycle after the sig_c.

(Q i223)o esig_ai mayobe qassertedre only iwhileoq jsig_bre is itrue, oi.e.,qwe arez atu yleaste oonezx cycle after a sig_c and havent seen a sig_d since then (except perhaps in the current cycle) www.testbench.in

(Q i224)o esig_ai mayobe qassertedre only iduringoq jthere time iframe obeginningqwith sig_bz (inclusive)u yande ocontinuingzx until sig_c rises (inclusive).

(Q i225)o esig_ai mustonot qrisere if iweoq jhavere seen isig_b oandqhavent seenz theu ynexte osig_czx yet (from the cycle after the sig_b until the cycle before the sig_c).

(Q i226)o eWhilei sig_aois qdown,re sig_b imayoq jrisere only iif osig_cqis down. .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n

(Q i227)o eIfi sig_aois qassertedre with isig_boq jinactive,re and isig_c owasqinactive inz theu ypreviouse ocyclezx and remains inactive in the next cycle, then sig_a must be deasserted in the next cycle.

(Q i228)o eIfi thereoare qarere two ioccurencesoq jofre sig_a irising owithqSTATE=active1, andz nou ysig_be ooccurszx between them, then within 3 cycles of the second rise of sig_a, START must occur. www.testbench.in

(Q i229)o eShowi aosequence qwithre 3 itransactionsoq j(inre which isig_a oisqasserted 3z times).

(Q i230)o eIfi theostate qmachinere reaches iSTATE=active1,oq jitre will ieventually oreachqSTATE=active2.

(Q i231)o esig_ai isoeventually qasserted,re after isig_boq jhasre fallen.

(Q i232)o esig_ai isoeventually qassertedre without isig_boq jindication,re after isig_c ohasqfallen.

(Q i233)o eIfi sig_aois qactive,re then isig_boq jwasre active i3 ocyclesqago. www.testbench.in

(Q i234)o eIfi sig_aois qactive,re then isig_boq jwasre active isomewhere oinqthe past.

(Q i235)o eIfi thereois qare sig_a, ifollowedoq jbyre 3 iconsecutive osig_b,qthen inz eachu yofe othezx 3 cycles the data written (DO) is equal to the data read (DI).

(Q i236)o eAlways,i ifoon q3re consecutive isig_a,oq jsig_bre appears, ithen oonqthe nextz sig_cu ycycle,e osig_azx holds.

(Q i237)o eEveryi sig_aomust qeventuallyre be iacknowledgedoq jbyre sig_b, iunless osig_cqappears

(Q i238)o esig_ai occurson qcyclesre after isig_b. www.testbench.in

(Q i239)o esig_ai andosig_b qarere environment isignals,oq jwhichre can ibe ogivenqat anyz time,u ybute oshouldzx never be given together.

(Q i240)o eIfi sig_aois qactive,re it imustoq jbere deactivated ione ocycleqafter sig_bz arrives.u yNotee othatzx sig_a may already be active when sig_b is asserted.

Functional Verification Questions
Functional Verification Questions 2
Test Your Systemverilog Skills 1
Test Your Systemverilog Skills 2
Test Your Systemverilog Skills 3
Test Your Systemverilog Skills 4
Test Your Sva Skills
Test Your Verilog Skills 1
Test Your Verilog Skills 2
Test Your Verilog Skills 3
Test Your Verilog Skills 4
Test Your Verilog Skills 5
Test Your Verilog Skills 6
Test Your Verilog Skills 7
Test Your Verilog Skills 8
Test Your Verilog Skills 9
Test Your Verilog Skills 10
Test Your Verilog Skills 11
Test Your Verilog Skills 12
Test Your Verilog Skills 13
Test Your Verilog Skills 14
Test Your Verilog Skills 15
Test Your Verilog Skills 16
Test Your Verilog Skills 17
Test Your Specman Skills 1
Test Your Specman Skills 2
Test Your Specman Skills 3
Test Your Specman Skills 4
Test Your Sta Skills 1
Test Your Sta Skills 2
Test Your Sta Skills 3
Test Your Sta Skills 4
Test Your Sta Skills 5
Test Your Sta Skills 6
Test Your Sta Skills 7
Test Your Dft Skills 1
Test Your Dft Skills 2
Test Your Dft Skills 3
Test Your Dft Skills 4
Test Your Uvm Ovm Skills

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