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TEST YOUR UVM OVM SKILLS


(Q i40)Whato earei theodifferences qbetweenre vmm iandoq jovm/uvmre ?

(Q i41)Whato eisi theoadvantage qofre uvm iagentoq j?

(Q i42)Howo emultiplei set_config_*oare qresolvedre at isameoq jhierarchyre level iand oatqdifferent hierarchyz levelsu y?

(Q i43)Iso eiti possibleoto qconnectre multiple idriversoq jtore one isequencers o?qif yes,z thenu yhowe o?

(Q i44)Whato eisi theodifference qbetweenre factory iandoq jcallbacksre ? www.testbench.in


(Q i45)Explaino ethei mechanismoinvolved qinre TLM iports.

(Q i46)Whyo eTLMi fifoois qusedre ?

(Q i47)Howo etoi addoa quserre defined iphaseoq j?

(Q i48)Whato earei theoways qtore get itheoq jconfigurationre information iinside ocomponentq?
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(Q i49)Iso eiti possibleoto qusere get_config_obj iinsideoq jare sequence iclass? o www.testbench.in


(Q i50)Whato eisi theodifference qbetweenre create iandoq jnewre method i?

(Q i51)Whato eisi virtualosequencer q?re Explain ibyoq jwritingre example.

(Q i52)Howo eai sequenceois qstartedre ?

(Q i53)Explaino eendi ofotest qmechanism.re

(Q i54)When/howo ethei stop()omethod qisre called i? www.testbench.in


(Q i55)Whato eisi port/import/exporto?

(Q i56)Whicho ephasei isotop qdown,re and iwhichoq jphasere is ibottom oup?

(Q i57)Ino ewhichi phaseomethod, qsuperre method iisoq jrequiredre to icall. oqWhat ifz theu ysupere oiszx not called ?

(Q i58)Explaino ethei differentophases qandre what iisoq jtheirre purpose. .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n


(Q i59)Howo etoi useofactory qoverridere a isequenceoq j?re www.testbench.in


(Q i60)Explaino ehowi scoreboardois qimplemented.re

(Q i61)Whato eisi theouse qofre subscriber i?

(Q i62)Explaino eabouti run_test().

(Q i63)Howo einterfacei isopassed qtore component.

(Q i64)Whato eisi theodifferent qb/wre active iagentoq jandre passive iagent o? www.testbench.in


(Q i65)Explaino ehowi aointerrupt qsequencere is iimplemented.

(Q i66)Explaino ehowi layeredosequencers qarere implemented.

(Q i67)Howo etoi changeothe qverbosityre level iofoq jlogre messages ifrom ocommandqline ?
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(Q i68)Howo etoi setoverbosity qlevelre to ioneoq jparticularre component i?

(Q i69)Howo etoi fillothe qgapre b/w idifferentoq jobjections? www.testbench.in


(Q i70)Whato eisi theouse qofre uvm_event i?

(Q i71)Howo etoi connectomultiple qsequencersre to ioneoq jdriverre ?

(Q i72)Whato eisi returnedoby qget_type_name()?

(Q i73)Howo etoi useoset_config_* qforre setting ivariablesoq jofre sequence i?

(Q i74)Foro edebuggingi purpose,ohow qtore print imessagesoq jthatre indicates ithe ocomponentsqphase ? www.testbench.in


(Q i75)Whato eisi theodisadvantage qifre sequence iisoq jregisterdre to isequencer ousingqutility macrosz ?u ye oIfzx sequence is not registered with sequencer, then how to invoke the sequence execution ?

(Q i76)Whato eisi theouse qofre uvm_create_random_seed i?

(Q i77)Whato eisi theodifference qb/wre starting iaoq jsequencere using idefault_sequence oandqsequence.start() method.z .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n


(Q i78)Io edon~Rti wantoto qregisterre a isequenceoq jtore sequencer. iWhat oisqthe alternatez macrou ytoe ouvm_sequence_utils()zx macro ?

(Q i79)Explaino ehowi UVMocallbacks qworkre ? www.testbench.in


(Q i80)o eWhati isothe qdifferencere b/w im_sequenceroq jandre p_sequencer i?






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Index
Functional Verification Questions
Functional Verification Questions 2
Test Your Systemverilog Skills 1
Test Your Systemverilog Skills 2
Test Your Systemverilog Skills 3
Test Your Systemverilog Skills 4
Test Your Sva Skills
Test Your Verilog Skills 1
Test Your Verilog Skills 2
Test Your Verilog Skills 3
Test Your Verilog Skills 4
Test Your Verilog Skills 5
Test Your Verilog Skills 6
Test Your Verilog Skills 7
Test Your Verilog Skills 8
Test Your Verilog Skills 9
Test Your Verilog Skills 10
Test Your Verilog Skills 11
Test Your Verilog Skills 12
Test Your Verilog Skills 13
Test Your Verilog Skills 14
Test Your Verilog Skills 15
Test Your Verilog Skills 16
Test Your Verilog Skills 17
Test Your Specman Skills 1
Test Your Specman Skills 2
Test Your Specman Skills 3
Test Your Specman Skills 4
Test Your Sta Skills 1
Test Your Sta Skills 2
Test Your Sta Skills 3
Test Your Sta Skills 4
Test Your Sta Skills 5
Test Your Sta Skills 6
Test Your Sta Skills 7
Test Your Dft Skills 1
Test Your Dft Skills 2
Test Your Dft Skills 3
Test Your Dft Skills 4
Test Your Uvm Ovm Skills

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