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TEST YOUR VERILOG SKILLS 3
(Q i39)o ei Whatois qthere difference ibetweenoq jstaticre function iand oautomaticqfunction?
Ans:
Automatic ifunctiono elocali variablesoCan qnotre seen iinoq jwavere form iviewer.
We icannoto eusei $Monitoroand q$strobere on ilocaloq jvariablesre also i.
(Q i40)o ei Whatois qthere difference ibetweenoq jstaticre task iand oautomaticqtask?
(Q i41)o eWhati isoadvantage qofre wand iandoq jworre over iwire o? www.testbench.in
Ans:
It isupporto eTechnology-dependenti logicoconflict qresolutionre . i
wired-AND iforo eopeni collector
wired-OR iforo eECL
(Q i42)o eIdentifyi theoerror qinre the ifollowingoq jcode.
a[7:0] i=o e{4{'b10}};
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i43)o eWhati isothe qdifferencere between i&&oq jandre &, iif oany? www.testbench.in
(Q i44)o eIsi itosynthesysable q?
always i@(negedgeo eclki ororst)
(Q i45)o eWhati isothe qdifferencere between iinitialoq jandre always iblock?
Ans:
NOTE: iInitialo eblocki canoalso qbere synthesized. iRefoq jtore IEEE iVerilog oSynthesisqslandered.
(Q i46)o ewhati isothe qdifferencere between i$stopoq jandre $finish itask ofunctions?
www.testbench.in
(Q i47)o eDifferencei betweenoparameter qandre define i?
(Q i48)o ei Whatothe qdifferencere between itheoq jfollowingre two istatements?
@( ivalo e==i 2)
wait(val i==o e2)
(Q i49)o eWhati areothe qdifferencere while ispecifyingoq jthere parameters iusing otheqdefparam constructz vs.u yspecifyinge oduringzx instantiation? .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i50)o ei Differenceobetween qVectoredre and iscalaredoq jnets? www.testbench.in
(Q i51)o ei Differenceobw qrealre and irealtimeoq j?
(Q i52)o ei whatois qthere difference ibetweenoq jarthamaticre and ilogical oshiftqregister?
(Q i53)o ei Whatois qthere difference ibwoq jfollowingre two iregisters??
reg i[1:n]o erega;i //oAn qn-bitre register iisoq jnotre the isame
reg imemao e[1:n];i //oas qare memory iofoq jnre 1-bit iregisters
www.testbench.in
(Q i54)o ei Howothe qabovere two iareoq jhandledre in i oassignments,qports,functions andz tasku y?
(Q i55)o ei Whatois qthere difference ibetweenoq jparametersre and ispecparams?
(Q i56)o eIsi itopossible qtore synthesize iforoq jloopre ?
Ans: .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
for iloopo ewithi fixedolimits qcanre be ioq jSynthesizedre
(Q i57)o eHowi isotime qadvancedre in iaoq jsimulation? www.testbench.in
(Q i58)o eNamei threeomethods qofre timing icontrol?
(Q i59)o eWhati isobehavioral qmodelingre used ifor?
(Q i60)o eHowi dooyou qdefinere the istatesoq jforre an iFSM?
(Q i61)o ei Whatois qthere difference ibetweenoq jforcere release iand oassignqdeassign?
(Q i62)o ei Whatois qthere difference ibetweenoq jposedgere and inegedge? o www.testbench.in
And:
A inegedgeo eshalli beodetected qonre the itransitionoq jfromre 1 ito ox,qz, orz 0,u yande ofromzx x or z to 0 where as posedge shall be detected on the transition from 0 to x, z, or 1, and from x or z to 1
(Q i63)o ei whatois qthere difference ibetweenoq j$displayre and i$write?
Ans: i
The itwoo esetsi ofotasks qarere identical iexceptoq jthatre $display iautomatically oaddsqa newlinez characteru ytoe othezx end of its output, whereas the $write task does not. The $display task, when invoked without arguments, simply prints a newline character. A $write task supplied without parameters prints nothing at all. .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i64)o ei Whatois qthere difference ibetweenoq j$displayre and i$monitor?
(Q i39)o ei Whatois qthere difference ibetweenoq jstaticre function iand oautomaticqfunction?
Ans:
Automatic ifunctiono elocali variablesoCan qnotre seen iinoq jwavere form iviewer.
We icannoto eusei $Monitoroand q$strobere on ilocaloq jvariablesre also i.
(Q i40)o ei Whatois qthere difference ibetweenoq jstaticre task iand oautomaticqtask?
(Q i41)o eWhati isoadvantage qofre wand iandoq jworre over iwire o? www.testbench.in
Ans:
It isupporto eTechnology-dependenti logicoconflict qresolutionre . i
wired-AND iforo eopeni collector
wired-OR iforo eECL
(Q i42)o eIdentifyi theoerror qinre the ifollowingoq jcode.
a[7:0] i=o e{4{'b10}};
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i43)o eWhati isothe qdifferencere between i&&oq jandre &, iif oany? www.testbench.in
(Q i44)o eIsi itosynthesysable q?
always i@(negedgeo eclki ororst)
(Q i45)o eWhati isothe qdifferencere between iinitialoq jandre always iblock?
Ans:
NOTE: iInitialo eblocki canoalso qbere synthesized. iRefoq jtore IEEE iVerilog oSynthesisqslandered.
(Q i46)o ewhati isothe qdifferencere between i$stopoq jandre $finish itask ofunctions?
www.testbench.in
(Q i47)o eDifferencei betweenoparameter qandre define i?
(Q i48)o ei Whatothe qdifferencere between itheoq jfollowingre two istatements?
@( ivalo e==i 2)
wait(val i==o e2)
(Q i49)o eWhati areothe qdifferencere while ispecifyingoq jthere parameters iusing otheqdefparam constructz vs.u yspecifyinge oduringzx instantiation? .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i50)o ei Differenceobetween qVectoredre and iscalaredoq jnets? www.testbench.in
(Q i51)o ei Differenceobw qrealre and irealtimeoq j?
(Q i52)o ei whatois qthere difference ibetweenoq jarthamaticre and ilogical oshiftqregister?
(Q i53)o ei Whatois qthere difference ibwoq jfollowingre two iregisters??
reg i[1:n]o erega;i //oAn qn-bitre register iisoq jnotre the isame
reg imemao e[1:n];i //oas qare memory iofoq jnre 1-bit iregisters
www.testbench.in
(Q i54)o ei Howothe qabovere two iareoq jhandledre in i oassignments,qports,functions andz tasku y?
(Q i55)o ei Whatois qthere difference ibetweenoq jparametersre and ispecparams?
(Q i56)o eIsi itopossible qtore synthesize iforoq jloopre ?
Ans: .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
for iloopo ewithi fixedolimits qcanre be ioq jSynthesizedre
(Q i57)o eHowi isotime qadvancedre in iaoq jsimulation? www.testbench.in
(Q i58)o eNamei threeomethods qofre timing icontrol?
(Q i59)o eWhati isobehavioral qmodelingre used ifor?
(Q i60)o eHowi dooyou qdefinere the istatesoq jforre an iFSM?
(Q i61)o ei Whatois qthere difference ibetweenoq jforcere release iand oassignqdeassign?
(Q i62)o ei Whatois qthere difference ibetweenoq jposedgere and inegedge? o www.testbench.in
And:
A inegedgeo eshalli beodetected qonre the itransitionoq jfromre 1 ito ox,qz, orz 0,u yande ofromzx x or z to 0 where as posedge shall be detected on the transition from 0 to x, z, or 1, and from x or z to 1
(Q i63)o ei whatois qthere difference ibetweenoq j$displayre and i$write?
Ans: i
The itwoo esetsi ofotasks qarere identical iexceptoq jthatre $display iautomatically oaddsqa newlinez characteru ytoe othezx end of its output, whereas the $write task does not. The $display task, when invoked without arguments, simply prints a newline character. A $write task supplied without parameters prints nothing at all. .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i64)o ei Whatois qthere difference ibetweenoq j$displayre and i$monitor?
Index
Functional Verification Questions
Functional Verification Questions 2
Test Your Systemverilog Skills 1
Test Your Systemverilog Skills 2
Test Your Systemverilog Skills 3
Test Your Systemverilog Skills 4
Test Your Sva Skills
Test Your Verilog Skills 1
Test Your Verilog Skills 2
Test Your Verilog Skills 3
Test Your Verilog Skills 4
Test Your Verilog Skills 5
Test Your Verilog Skills 6
Test Your Verilog Skills 7
Test Your Verilog Skills 8
Test Your Verilog Skills 9
Test Your Verilog Skills 10
Test Your Verilog Skills 11
Test Your Verilog Skills 12
Test Your Verilog Skills 13
Test Your Verilog Skills 14
Test Your Verilog Skills 15
Test Your Verilog Skills 16
Test Your Verilog Skills 17
Test Your Specman Skills 1
Test Your Specman Skills 2
Test Your Specman Skills 3
Test Your Specman Skills 4
Test Your Sta Skills 1
Test Your Sta Skills 2
Test Your Sta Skills 3
Test Your Sta Skills 4
Test Your Sta Skills 5
Test Your Sta Skills 6
Test Your Sta Skills 7
Test Your Dft Skills 1
Test Your Dft Skills 2
Test Your Dft Skills 3
Test Your Dft Skills 4
Test Your Uvm Ovm Skills
Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!
Functional Verification Questions
Functional Verification Questions 2
Test Your Systemverilog Skills 1
Test Your Systemverilog Skills 2
Test Your Systemverilog Skills 3
Test Your Systemverilog Skills 4
Test Your Sva Skills
Test Your Verilog Skills 1
Test Your Verilog Skills 2
Test Your Verilog Skills 3
Test Your Verilog Skills 4
Test Your Verilog Skills 5
Test Your Verilog Skills 6
Test Your Verilog Skills 7
Test Your Verilog Skills 8
Test Your Verilog Skills 9
Test Your Verilog Skills 10
Test Your Verilog Skills 11
Test Your Verilog Skills 12
Test Your Verilog Skills 13
Test Your Verilog Skills 14
Test Your Verilog Skills 15
Test Your Verilog Skills 16
Test Your Verilog Skills 17
Test Your Specman Skills 1
Test Your Specman Skills 2
Test Your Specman Skills 3
Test Your Specman Skills 4
Test Your Sta Skills 1
Test Your Sta Skills 2
Test Your Sta Skills 3
Test Your Sta Skills 4
Test Your Sta Skills 5
Test Your Sta Skills 6
Test Your Sta Skills 7
Test Your Dft Skills 1
Test Your Dft Skills 2
Test Your Dft Skills 3
Test Your Dft Skills 4
Test Your Uvm Ovm Skills
Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!