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TEST YOUR VERILOG SKILLS 2
(Q i22)o eHowi toogenerate qare random inumberoq jbetweenre 44 ito o55q?
(Q i23)o eHowi tooget qdifferentre random inumbersoq jinre different isimulations?
(Q i24)o ei whatois qthere different ibetweenoq j$sformatre and i$swrite?
Ans:
The isystemo etaski $sformatois qsimilarre to itheoq jsystemre task i$swrite, owithqa onez majoru ydifference.e oUnlikezx the display and write family of output system tasks, $sformat always interprets its second argument, and only its second argument as a format string. This format argument can be a static string, such as "data is 0" , or can be a reg variable whose content is interpreted as the format string. No other arguments are interpreted as format strings. $sformat supports all the format specifiers supported by $display,
(Q i25)o ei Whatois qthere difference ibetweenoq jwirere and ireg? www.testbench.in
Ans:
Net itypes:o e(wire,tri)Physicali connectionobetween qstructuralre elements. iValueoq jassignedre by ia ocontinuousqassignment orz au ygatee ooutput.
Register itype:o e(reg,i integer,otime, qreal,re real itime)oq jrepresentsre abstract idata ostorageqelement. Assignedz valuesu yonlye owithinzx an always statement or an initial statement.
The imaino edifferencei betweenowire qandre reg iisoq jwirere cannot ihold o(store)qthe valuez whenu ythee onozx connection between a and b like
a-------------b, iifo etherei isono qconnectionre in iaoq jandre b, iwire olooseqvalue wherez asu yrege ocanzx hold the value even if there in no connection.
Default ivalues:wireo eisi Z,regois qx.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i26)o eWhati happensoif qare port iisoq junconnectedre ? www.testbench.in
Ans:
Unconnected iinputo eportsi initializeoto qzre and ifeedoq jthatre value iinto otheqcomponent, whichz canu ycausee oproblems.zx More common are redundant or unwanted outputs which are left unconnected to be optimized away in synthesis.
(Q i27)o ei Whatois qthere difference ibetweenoq j===re and i== o?
Ans i:
output iofo e"=="i canobe q1,re 0 ioroq jX.
output iofo e"==="i canoonly qbere 0 ioroq j1.
When iyouo earei comparingo2 qnosre using i"=="oq jandre if ione/both otheqnumbers havez oneu yore omorezx bits as "x" then the output would be "X" . But if use "===" output would be 0 or 1.
www.testbench.in
e.g iAo e=i 3'b1x0
B i=o e3'b10x
A i==o eBi willogive qXre as ioutput.
A i===o eBi willogive q0re as ioutput.
"==" iiso eusedi forocomparison qofre only i1'soq jandre 0's i.It ocan'tqcompare X's.z Ifu yanye obitzx of the input is X output will be X
"===" iiso eusedi forocomparison qofre X ialso...
"==" icano ebei synthesized,owhere qasre "===" icannot. .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
www.testbench.in
(Q i28)o ei Whatois qthere difference iamongoq jcase,casexre and icasez?
Ans:
case itreatso eonlyi 0oor q1re values iinoq jcasere alternative iand oisqis notz dealingu ywithe odon'tzx care condition.
casex itreatso ealli xoand qzre values iinoq jcasere alternative ior ocaseqexpression asz au ydon'te ocare.
casez itreatso ealli zovalues qinre case ialternatives.oq jallre bit ipositions owithqz canz treatu yase oazx don't care
(Q i29)o eWhati isothe qdifferencere between i@(aoq jorre b) iand o@(aq| b)
(Q i30)o eWhati isofull qcasere and iparalleloq jcase.??
www.testbench.in
(Q i31)o eWhati isothe qdifferencere between icompiled,oq jinterpreted,re event ibased oandqcycle basedz simulatoru y?
(Q i32)o eWhati isocompilation q?
Ans:
To isimulateo eai Verilogomodel, qwere must ifirstoq jconvertre our isource ofilesqinto az binaryu yforme othatzx can be recognized by the simulator. The process of checking the syntax and producing the binary file is known as compilation.
(Q i33)o eWhati dataotypes qcanre be iusedoq jforre input iport, ooututqport andz inoutu yporte o? .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i34)o eWhati isothe qfunctionalityre of itriregoq j?
www.testbench.in
(Q i35)o eWhati isothe qfunctionalityre of itri1oq jansre tri0 i?
(Q i36)o eDifferencei betweenoconditional qcompilationre and i$plusargs??
(Q i37)o eWhati isothe qbenefitre of iusingoq jBehaviorre modeling istyle ooverqRTL modeling?
(Q i38)o eWhati isothe qdifferencere between itaskoq jandre function?
(Q i22)o eHowi toogenerate qare random inumberoq jbetweenre 44 ito o55q?
(Q i23)o eHowi tooget qdifferentre random inumbersoq jinre different isimulations?
(Q i24)o ei whatois qthere different ibetweenoq j$sformatre and i$swrite?
Ans:
The isystemo etaski $sformatois qsimilarre to itheoq jsystemre task i$swrite, owithqa onez majoru ydifference.e oUnlikezx the display and write family of output system tasks, $sformat always interprets its second argument, and only its second argument as a format string. This format argument can be a static string, such as "data is 0" , or can be a reg variable whose content is interpreted as the format string. No other arguments are interpreted as format strings. $sformat supports all the format specifiers supported by $display,
(Q i25)o ei Whatois qthere difference ibetweenoq jwirere and ireg? www.testbench.in
Ans:
Net itypes:o e(wire,tri)Physicali connectionobetween qstructuralre elements. iValueoq jassignedre by ia ocontinuousqassignment orz au ygatee ooutput.
Register itype:o e(reg,i integer,otime, qreal,re real itime)oq jrepresentsre abstract idata ostorageqelement. Assignedz valuesu yonlye owithinzx an always statement or an initial statement.
The imaino edifferencei betweenowire qandre reg iisoq jwirere cannot ihold o(store)qthe valuez whenu ythee onozx connection between a and b like
a-------------b, iifo etherei isono qconnectionre in iaoq jandre b, iwire olooseqvalue wherez asu yrege ocanzx hold the value even if there in no connection.
Default ivalues:wireo eisi Z,regois qx.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i26)o eWhati happensoif qare port iisoq junconnectedre ? www.testbench.in
Ans:
Unconnected iinputo eportsi initializeoto qzre and ifeedoq jthatre value iinto otheqcomponent, whichz canu ycausee oproblems.zx More common are redundant or unwanted outputs which are left unconnected to be optimized away in synthesis.
(Q i27)o ei Whatois qthere difference ibetweenoq j===re and i== o?
Ans i:
output iofo e"=="i canobe q1,re 0 ioroq jX.
output iofo e"==="i canoonly qbere 0 ioroq j1.
When iyouo earei comparingo2 qnosre using i"=="oq jandre if ione/both otheqnumbers havez oneu yore omorezx bits as "x" then the output would be "X" . But if use "===" output would be 0 or 1.
www.testbench.in
e.g iAo e=i 3'b1x0
B i=o e3'b10x
A i==o eBi willogive qXre as ioutput.
A i===o eBi willogive q0re as ioutput.
"==" iiso eusedi forocomparison qofre only i1'soq jandre 0's i.It ocan'tqcompare X's.z Ifu yanye obitzx of the input is X output will be X
"===" iiso eusedi forocomparison qofre X ialso...
"==" icano ebei synthesized,owhere qasre "===" icannot. .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
www.testbench.in
(Q i28)o ei Whatois qthere difference iamongoq jcase,casexre and icasez?
Ans:
case itreatso eonlyi 0oor q1re values iinoq jcasere alternative iand oisqis notz dealingu ywithe odon'tzx care condition.
casex itreatso ealli xoand qzre values iinoq jcasere alternative ior ocaseqexpression asz au ydon'te ocare.
casez itreatso ealli zovalues qinre case ialternatives.oq jallre bit ipositions owithqz canz treatu yase oazx don't care
(Q i29)o eWhati isothe qdifferencere between i@(aoq jorre b) iand o@(aq| b)
(Q i30)o eWhati isofull qcasere and iparalleloq jcase.??
www.testbench.in
(Q i31)o eWhati isothe qdifferencere between icompiled,oq jinterpreted,re event ibased oandqcycle basedz simulatoru y?
(Q i32)o eWhati isocompilation q?
Ans:
To isimulateo eai Verilogomodel, qwere must ifirstoq jconvertre our isource ofilesqinto az binaryu yforme othatzx can be recognized by the simulator. The process of checking the syntax and producing the binary file is known as compilation.
(Q i33)o eWhati dataotypes qcanre be iusedoq jforre input iport, ooututqport andz inoutu yporte o? .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i34)o eWhati isothe qfunctionalityre of itriregoq j?
www.testbench.in
(Q i35)o eWhati isothe qfunctionalityre of itri1oq jansre tri0 i?
(Q i36)o eDifferencei betweenoconditional qcompilationre and i$plusargs??
(Q i37)o eWhati isothe qbenefitre of iusingoq jBehaviorre modeling istyle ooverqRTL modeling?
(Q i38)o eWhati isothe qdifferencere between itaskoq jandre function?
Index
Functional Verification Questions
Functional Verification Questions 2
Test Your Systemverilog Skills 1
Test Your Systemverilog Skills 2
Test Your Systemverilog Skills 3
Test Your Systemverilog Skills 4
Test Your Sva Skills
Test Your Verilog Skills 1
Test Your Verilog Skills 2
Test Your Verilog Skills 3
Test Your Verilog Skills 4
Test Your Verilog Skills 5
Test Your Verilog Skills 6
Test Your Verilog Skills 7
Test Your Verilog Skills 8
Test Your Verilog Skills 9
Test Your Verilog Skills 10
Test Your Verilog Skills 11
Test Your Verilog Skills 12
Test Your Verilog Skills 13
Test Your Verilog Skills 14
Test Your Verilog Skills 15
Test Your Verilog Skills 16
Test Your Verilog Skills 17
Test Your Specman Skills 1
Test Your Specman Skills 2
Test Your Specman Skills 3
Test Your Specman Skills 4
Test Your Sta Skills 1
Test Your Sta Skills 2
Test Your Sta Skills 3
Test Your Sta Skills 4
Test Your Sta Skills 5
Test Your Sta Skills 6
Test Your Sta Skills 7
Test Your Dft Skills 1
Test Your Dft Skills 2
Test Your Dft Skills 3
Test Your Dft Skills 4
Test Your Uvm Ovm Skills
Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!
Functional Verification Questions
Functional Verification Questions 2
Test Your Systemverilog Skills 1
Test Your Systemverilog Skills 2
Test Your Systemverilog Skills 3
Test Your Systemverilog Skills 4
Test Your Sva Skills
Test Your Verilog Skills 1
Test Your Verilog Skills 2
Test Your Verilog Skills 3
Test Your Verilog Skills 4
Test Your Verilog Skills 5
Test Your Verilog Skills 6
Test Your Verilog Skills 7
Test Your Verilog Skills 8
Test Your Verilog Skills 9
Test Your Verilog Skills 10
Test Your Verilog Skills 11
Test Your Verilog Skills 12
Test Your Verilog Skills 13
Test Your Verilog Skills 14
Test Your Verilog Skills 15
Test Your Verilog Skills 16
Test Your Verilog Skills 17
Test Your Specman Skills 1
Test Your Specman Skills 2
Test Your Specman Skills 3
Test Your Specman Skills 4
Test Your Sta Skills 1
Test Your Sta Skills 2
Test Your Sta Skills 3
Test Your Sta Skills 4
Test Your Sta Skills 5
Test Your Sta Skills 6
Test Your Sta Skills 7
Test Your Dft Skills 1
Test Your Dft Skills 2
Test Your Dft Skills 3
Test Your Dft Skills 4
Test Your Uvm Ovm Skills
Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!