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TEST YOUR VERILOG SKILLS 6
(Q i106)o ei Findothe qbugre in itheoq jfollowingre code.
for(............);
begin
.....
end
Ans:
Misplaced isemicolonso eini for-loops
www.testbench.in
(Q i107)o ei Findothe qbugre in itheoq jfollowingre code.
automatic itasko eintra_assign();
begin
a i<=o e#10i b;
end
ANS:
Intra iassignmento enonblockingi statementsoare qnotre allowed iinoq jautomaticre tasks.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i108)o ei Findothe qbugre in itheoq jfollowingre code. www.testbench.in
always i@o e(in)
if i(ena)
out i=o ein;
else
out i=o e1~Rb1;
Ans:
simulation imismatcho emighti occur.
To iassureo ethei simulationowill qmatchre the isynthesizedoq jlogic,re add i"ena" otoqthe eventz listu ysoe othezx event list reads: always @ (in or ena)
www.testbench.in
(Q i109)o ei Findothe qbugre in itheoq jfollowingre code.
always i@o e(in1i oroin2 qorre sel)
begin
out i=o ein1;
if i(sel)
out i<=o ein2;
end
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Ans:
Not isupported,o ecannoti mixoblocking qandre nonblocking iassignmentsoq jinre an ialways ostatement. www.testbench.in
(Q i110)o ei Findothe qbugre in itheoq jfollowingre code.
reg i[1:0]o eselect;
always@(select)
begin
case i(select)
00: iyo e=i 1;
01: iyo e=i 2;
10: iyo e=i 3;
11: iyo e=i 4; www.testbench.in
endcase
end
Ans:
branches i01o eandi 11oare qconsideredre as iintegersoq jandre they iwill oneverqbe selected.
(Q i111)o ei Fillothe q???? .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
fd i=o e$fopen("filename",r);
if(????) www.testbench.in
$display("file icannoto ebei opened");
(Q i112)o ei Howoto qmodelre a iperfectoq jbufferre of i10units odelay?
a) i#10o eai =ob;
b) iao e=i #10ob;
c)#10 iao e<=i b;
d) iao e<=i #10ob;
(Q i113)o eWhati isoverilog qconfiguration? www.testbench.in
(Q i114)o eWritei aocode qforre clock igenerator.
(Q i115)o eWritei aocode qforre clock igeneratoroq jwhichre can igenerate oclockqfrequency ofz 156MHZ.
(Q i116)o ewritei aoverilog qcodere to igenerateoq j40MHzre clock iwith o60q0uty cycle .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i117)o eWhati pointsoneed qtore be iconsideredoq jwhilere writing ia oclockqgenerator???
(Q i118)o eExplaini verilogoevent qqueue. www.testbench.in
(Q i119)o ehowi theoscope qofre a ivariableoq jisre realized iin overilog.qIllustrate withz example.?
(Q i120)o eWhati isoincremental qcompilation?
(Q i121)o eWhati isoPLI?
Ans:
PLI iiso eai mechanismoto qinvokere C isubroutinesoq jtore Verilog. i
(Q i122)o eIni whatoregion qofre the ieventoq jqueuere , iPLI ocallsqare executed? www.testbench.in
(Q i123)o eWhati isocalltf qinre Verilog iPLI?
Ans:
Calltf iiso esimilari toomain() qfunctionre in iC.oq jre calltf ican ocallqother subz methodsu ytoe odifferentzx jobs.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i124)o eWhati isothe qdifferencere between iParalleloq jandre Full iConnection oModuleqPath delaysz ?
Ans:
A iparallelo econnectioni establishesoa qconnectionre between ieachoq jbitre in ithe osourceqto eachz correspondingu ybite oinzx the destination. Parallel module paths can be created only between one source and one destination where each signal contains the same number of bits.
www.testbench.in
A ifullo econnectioni establishesoa qconnectionre between ieveryoq jbitre in ithe osourceqand everyz bitu yine othezx destination. The module path source does not need to have the same number of bits as the module path destination.
(Q i125)o eCani $setupoand q$holdre check ireportoq jare violation ifor oaqlimit ofz zero?
(Q i126)o eExplaini abouto$recovery qandre $removal i?
(Q i127)o eWhichi timingocheck(s) qacceptre a inegativeoq jlimit?
(Q i128)o eCani youoqualify qallre events iinoq jallre timing ichecks owithqedge specifiersz suchu yase oedgezx 01? www.testbench.in
(Q i129)o eFori whichotiming qcheck(s)re must iyouoq jalwaysre qualify ievents?
(Q i130)o eWheni doeso$skew qreportre a iviolation? .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i131)o eWhati isomisctf q?
Ans:
Misctf iiso etoi doohousekeeping qjobs.re This iisoq jcanre be icalled omanyqtimes unlikez otheru ypredefinede ofunctionszx which are called once per instance.
www.testbench.in
(Q i132)o ei o qre ioq jre iWhat oisqUDP? Canz weu ywritee oUDPzx including clock also?
(Q i133)o eHowi dooI qpreventre selected iparametersoq jofre a imodule ofromqbeing overriddenz duringu yinstantiation?
(Q i106)o ei Findothe qbugre in itheoq jfollowingre code.
for(............);
begin
.....
end
Ans:
Misplaced isemicolonso eini for-loops
www.testbench.in
(Q i107)o ei Findothe qbugre in itheoq jfollowingre code.
automatic itasko eintra_assign();
begin
a i<=o e#10i b;
end
ANS:
Intra iassignmento enonblockingi statementsoare qnotre allowed iinoq jautomaticre tasks.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i108)o ei Findothe qbugre in itheoq jfollowingre code. www.testbench.in
always i@o e(in)
if i(ena)
out i=o ein;
else
out i=o e1~Rb1;
Ans:
simulation imismatcho emighti occur.
To iassureo ethei simulationowill qmatchre the isynthesizedoq jlogic,re add i"ena" otoqthe eventz listu ysoe othezx event list reads: always @ (in or ena)
www.testbench.in
(Q i109)o ei Findothe qbugre in itheoq jfollowingre code.
always i@o e(in1i oroin2 qorre sel)
begin
out i=o ein1;
if i(sel)
out i<=o ein2;
end
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Ans:
Not isupported,o ecannoti mixoblocking qandre nonblocking iassignmentsoq jinre an ialways ostatement. www.testbench.in
(Q i110)o ei Findothe qbugre in itheoq jfollowingre code.
reg i[1:0]o eselect;
always@(select)
begin
case i(select)
00: iyo e=i 1;
01: iyo e=i 2;
10: iyo e=i 3;
11: iyo e=i 4; www.testbench.in
endcase
end
Ans:
branches i01o eandi 11oare qconsideredre as iintegersoq jandre they iwill oneverqbe selected.
(Q i111)o ei Fillothe q???? .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
fd i=o e$fopen("filename",r);
if(????) www.testbench.in
$display("file icannoto ebei opened");
(Q i112)o ei Howoto qmodelre a iperfectoq jbufferre of i10units odelay?
a) i#10o eai =ob;
b) iao e=i #10ob;
c)#10 iao e<=i b;
d) iao e<=i #10ob;
(Q i113)o eWhati isoverilog qconfiguration? www.testbench.in
(Q i114)o eWritei aocode qforre clock igenerator.
(Q i115)o eWritei aocode qforre clock igeneratoroq jwhichre can igenerate oclockqfrequency ofz 156MHZ.
(Q i116)o ewritei aoverilog qcodere to igenerateoq j40MHzre clock iwith o60q0uty cycle .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i117)o eWhati pointsoneed qtore be iconsideredoq jwhilere writing ia oclockqgenerator???
(Q i118)o eExplaini verilogoevent qqueue. www.testbench.in
(Q i119)o ehowi theoscope qofre a ivariableoq jisre realized iin overilog.qIllustrate withz example.?
(Q i120)o eWhati isoincremental qcompilation?
(Q i121)o eWhati isoPLI?
Ans:
PLI iiso eai mechanismoto qinvokere C isubroutinesoq jtore Verilog. i
(Q i122)o eIni whatoregion qofre the ieventoq jqueuere , iPLI ocallsqare executed? www.testbench.in
(Q i123)o eWhati isocalltf qinre Verilog iPLI?
Ans:
Calltf iiso esimilari toomain() qfunctionre in iC.oq jre calltf ican ocallqother subz methodsu ytoe odifferentzx jobs.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i124)o eWhati isothe qdifferencere between iParalleloq jandre Full iConnection oModuleqPath delaysz ?
Ans:
A iparallelo econnectioni establishesoa qconnectionre between ieachoq jbitre in ithe osourceqto eachz correspondingu ybite oinzx the destination. Parallel module paths can be created only between one source and one destination where each signal contains the same number of bits.
www.testbench.in
A ifullo econnectioni establishesoa qconnectionre between ieveryoq jbitre in ithe osourceqand everyz bitu yine othezx destination. The module path source does not need to have the same number of bits as the module path destination.
(Q i125)o eCani $setupoand q$holdre check ireportoq jare violation ifor oaqlimit ofz zero?
(Q i126)o eExplaini abouto$recovery qandre $removal i?
(Q i127)o eWhichi timingocheck(s) qacceptre a inegativeoq jlimit?
(Q i128)o eCani youoqualify qallre events iinoq jallre timing ichecks owithqedge specifiersz suchu yase oedgezx 01? www.testbench.in
(Q i129)o eFori whichotiming qcheck(s)re must iyouoq jalwaysre qualify ievents?
(Q i130)o eWheni doeso$skew qreportre a iviolation? .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i131)o eWhati isomisctf q?
Ans:
Misctf iiso etoi doohousekeeping qjobs.re This iisoq jcanre be icalled omanyqtimes unlikez otheru ypredefinede ofunctionszx which are called once per instance.
www.testbench.in
(Q i132)o ei o qre ioq jre iWhat oisqUDP? Canz weu ywritee oUDPzx including clock also?
(Q i133)o eHowi dooI qpreventre selected iparametersoq jofre a imodule ofromqbeing overriddenz duringu yinstantiation?
Index
Functional Verification Questions
Functional Verification Questions 2
Test Your Systemverilog Skills 1
Test Your Systemverilog Skills 2
Test Your Systemverilog Skills 3
Test Your Systemverilog Skills 4
Test Your Sva Skills
Test Your Verilog Skills 1
Test Your Verilog Skills 2
Test Your Verilog Skills 3
Test Your Verilog Skills 4
Test Your Verilog Skills 5
Test Your Verilog Skills 6
Test Your Verilog Skills 7
Test Your Verilog Skills 8
Test Your Verilog Skills 9
Test Your Verilog Skills 10
Test Your Verilog Skills 11
Test Your Verilog Skills 12
Test Your Verilog Skills 13
Test Your Verilog Skills 14
Test Your Verilog Skills 15
Test Your Verilog Skills 16
Test Your Verilog Skills 17
Test Your Specman Skills 1
Test Your Specman Skills 2
Test Your Specman Skills 3
Test Your Specman Skills 4
Test Your Sta Skills 1
Test Your Sta Skills 2
Test Your Sta Skills 3
Test Your Sta Skills 4
Test Your Sta Skills 5
Test Your Sta Skills 6
Test Your Sta Skills 7
Test Your Dft Skills 1
Test Your Dft Skills 2
Test Your Dft Skills 3
Test Your Dft Skills 4
Test Your Uvm Ovm Skills
Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!
Functional Verification Questions
Functional Verification Questions 2
Test Your Systemverilog Skills 1
Test Your Systemverilog Skills 2
Test Your Systemverilog Skills 3
Test Your Systemverilog Skills 4
Test Your Sva Skills
Test Your Verilog Skills 1
Test Your Verilog Skills 2
Test Your Verilog Skills 3
Test Your Verilog Skills 4
Test Your Verilog Skills 5
Test Your Verilog Skills 6
Test Your Verilog Skills 7
Test Your Verilog Skills 8
Test Your Verilog Skills 9
Test Your Verilog Skills 10
Test Your Verilog Skills 11
Test Your Verilog Skills 12
Test Your Verilog Skills 13
Test Your Verilog Skills 14
Test Your Verilog Skills 15
Test Your Verilog Skills 16
Test Your Verilog Skills 17
Test Your Specman Skills 1
Test Your Specman Skills 2
Test Your Specman Skills 3
Test Your Specman Skills 4
Test Your Sta Skills 1
Test Your Sta Skills 2
Test Your Sta Skills 3
Test Your Sta Skills 4
Test Your Sta Skills 5
Test Your Sta Skills 6
Test Your Sta Skills 7
Test Your Dft Skills 1
Test Your Dft Skills 2
Test Your Dft Skills 3
Test Your Dft Skills 4
Test Your Uvm Ovm Skills
Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!