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Specman E
Interview Questions
TEST YOUR DFT SKILLS 1
"
The
i
greatest
o
e
of
i
all
o
faults
q
is
r
e
to
i
be
o
q
j
conscious
r
e
of
i
none
"
(Q
i
1)
o
e
What
i
is
o
q
DFT
r
e
?
Ans:
DFT
i
stands
o
e
for
i
Design
o
for
q
Testability.
r
e
To
i
check
o
q
j
manufacturing
r
e
defect
i
we
o
use
q
DFT.
www.testbench.in
(Q
i
2)
o
e
Techniques
i
of
o
DFT..!
Ans:
AD-Hock
i
techniques.
o
e
Structured
i
design
o
e
techniques
Self-test
i
+
o
e
Built-In
i
testing
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q
i
3)
o
e
Difference
i
between
o
verification
q
and
r
e
DFT
i
?
www.testbench.in
Ans.
i
Verification
o
e
attempt
i
to
o
prove
q
mathematically
r
e
that
i
certain
o
q
j
requirements
r
e
are
i
met
o
or
q
that certain
z
undesired
u
y
behaviors
e
o
cannot
z
x
occur while DFT checks the physical defect It has not concern with functionality.
(Q
i
4)
o
e
Wire
i
load
o
model
q
?
Ans.
i
It
o
e
is
i
statical
o
value
q
of
r
e
R
i
and
o
q
j
C,
r
e
for
i
which
o
library
q
file comes
z
from
u
y
the
e
o
fab.
(Q
i
5)
o
e
DRV,
i
DV,
o
GV,
q
SV
r
e
or
i
LVS.
Ans.
i
Physical
o
e
verification
i
has
o
two
q
parts:
r
e
DRC
i
check
o
q
j
and
r
e
schematic
i
verification
o
(SV).
www.testbench.in
i
o
e
i
o
q
DRV
r
e
-
i
Design
o
q
j
Rule
r
e
Violation
i
o
e
i
o
q
DV
r
e
-
i
Design
o
q
j
Rule
r
e
Verification
i
o
e
i
o
q
GV
r
e
-
i
Geometry
o
q
j
Violation
i
o
e
i
i
o
e
All
i
the
o
three
q
terms
r
e
point
i
to
o
q
j
the
r
e
same
i
process
o
of
q
checking that
z
the
u
y
layout
e
o
is
z
x
compliant with manufacture rules.
i
o
e
i
o
q
r
e
i
o
q
j
r
e
a.Active-to-active
i
spacing
i
o
e
i
o
q
r
e
i
o
q
j
r
e
b.Well-to-well
i
spacing
i
o
e
i
o
q
r
e
i
o
q
j
r
e
c.Minimum
i
channel
o
length
q
of the
z
transistor
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
i
o
e
i
o
q
r
e
i
o
q
j
r
e
d.Minimum
i
metal
o
width
i
o
e
i
o
q
r
e
i
o
q
j
r
e
e.Metal-to-metal
i
spacing
www.testbench.in
i
o
e
i
o
q
r
e
i
o
q
j
r
e
f.Metal
i
fill
o
density
i
o
e
i
o
q
SV
r
e
-
i
Scmatic
o
q
j
Violation
r
e
or
i
LVS
o
-
q
Layout versus
z
schematic
i
o
e
i
o
q
The
r
e
other
i
part
o
q
j
of
r
e
physical
i
verification
o
is
q
the schematic/netlist
z
check.
u
y
It
e
o
is
z
x
referred to as schematic verification (SV) or layout versus schematic (LVS).
i
o
e
i
o
q
Both
r
e
terms
i
describe
o
q
j
the
r
e
process
i
of
o
validating
q
that the
z
layout
u
y
matches
e
o
the
z
x
netlist/schematic.
i
o
e
i
o
q
i
o
e
i
o
q
r
e
i
a.shorts
i
o
e
i
o
q
r
e
i
b.opens
i
o
e
i
o
q
r
e
i
c.component
o
q
j
missing
i
o
e
i
o
q
r
e
i
d.mismatch
o
q
j
of
r
e
component
www.testbench.in
i
o
e
i
o
q
r
e
i
e.property
o
q
j
errors
(Q
i
6)
o
e
Tape
i
out
o
?
Ans.
i
Tapeout
o
e
is
i
the
o
final
q
step
r
e
of
i
chip
o
q
j
design.
r
e
It
i
is
o
the
q
time at
z
which
u
y
the
e
o
design
z
x
is fully qualified and ready for manufacturing. After the physical design is finished, the functionality of the netlist is verified, and the timing analysis is satisfied, the final layout, usually in GDSII (Gerber data stream information interchange) format, is sent to mask shop to generate photomask reticles. The resultant masks will be used to direct the manufacture of this chip.
(Q
i
7)
o
e
Need
i
of
o
DFT
q
?
r
e
Ans:
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
After
i
the
o
e
manufacturing
i
to
o
check
q
whether
r
e
actual
i
behavor
o
q
j
matches
r
e
the
i
expected
o
behavior
q
or not,
z
DFT
u
y
is
e
o
used.
www.testbench.in
(Q
i
8)
o
e
What
i
will
o
happen
q
if
r
e
manufactured
i
chip
o
q
j
is
r
e
not
i
working
o
functionality
q
?
Ans:
It
i
need
o
e
to
i
garbage.
(Q
i
9)
o
e
Yield
i
?
Ans:
Ratio
i
in
o
e
percentage
i
of
o
number
q
of
r
e
working
i
chips
o
q
j
to
r
e
total
i
no
o
chips
q
in single
z
u
y
wafer.
www.testbench.in
(Q
i
10)
o
e
Controllability
i
?
Ans:
Controllability
i
measures
o
e
the
i
ability
o
to
q
control
r
e
the
i
internal
o
q
j
state
r
e
of
i
the
o
circuit
q
through primary
z
inputs.
u
y
or
e
o
The
z
x
ability to set or reset internal nodes from the primary inputs.
(Q
i
11)
o
e
Observability
i
?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Ans:
Observability
i
measures
o
e
the
i
ability
o
to
q
observe
r
e
the
i
internal
o
q
j
state
r
e
of
i
the
o
circuit
q
through primary
z
outputs.
u
y
or
e
o
The
z
x
ability to observe the value of an internal node at the primary outputs
www.testbench.in
(Q
i
12)
o
e
How
i
to
o
drive
q
test
r
e
pattern
i
?
The
i
tests
o
e
generally
i
are
o
driven
q
by
r
e
test
i
programs
o
q
j
that
r
e
execute
i
in
o
Automatic
q
Test Equipment
z
(ATE).
Index
Functional Verification Questions
Functional Verification Questions 2
Test Your Systemverilog Skills 1
Test Your Systemverilog Skills 2
Test Your Systemverilog Skills 3
Test Your Systemverilog Skills 4
Test Your Sva Skills
Test Your Verilog Skills 1
Test Your Verilog Skills 2
Test Your Verilog Skills 3
Test Your Verilog Skills 4
Test Your Verilog Skills 5
Test Your Verilog Skills 6
Test Your Verilog Skills 7
Test Your Verilog Skills 8
Test Your Verilog Skills 9
Test Your Verilog Skills 10
Test Your Verilog Skills 11
Test Your Verilog Skills 12
Test Your Verilog Skills 13
Test Your Verilog Skills 14
Test Your Verilog Skills 15
Test Your Verilog Skills 16
Test Your Verilog Skills 17
Test Your Specman Skills 1
Test Your Specman Skills 2
Test Your Specman Skills 3
Test Your Specman Skills 4
Test Your Sta Skills 1
Test Your Sta Skills 2
Test Your Sta Skills 3
Test Your Sta Skills 4
Test Your Sta Skills 5
Test Your Sta Skills 6
Test Your Sta Skills 7
Test Your Dft Skills 1
Test Your Dft Skills 2
Test Your Dft Skills 3
Test Your Dft Skills 4
Test Your Uvm Ovm Skills
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