"The igreatesto eofi allofaults qisre to ibeoq jconsciousre of inone"

(Q i1)o eWhati iso qDFTre ?

DFT istandso efori Designofor qTestability.re To icheckoq jmanufacturingre defect iwe ouseqDFT.

(Q i2)o eTechniquesi ofoDFT..!

AD-Hock itechniques.o e
Structured idesigno etechniques
Self-test i+o eBuilt-Ini testing


(Q i3)o eDifferencei betweenoverification qandre DFT i? www.testbench.in


iVerificationo eattempti tooprove qmathematicallyre that icertainoq jrequirementsre are imet oorqthat certainz undesiredu ybehaviorse ocannotzx occur while DFT checks the physical defect It has not concern with functionality.

(Q i4)o eWirei loadomodel q?

iIto eisi staticalovalue qofre R iandoq jC,re for iwhich olibraryqfile comesz fromu ythee ofab.

(Q i5)o eDRV,i DV,oGV, qSVre or iLVS.

iPhysicalo everificationi hasotwo qparts:re DRC icheckoq jandre schematic iverification o(SV). www.testbench.in

io ei o qDRVre - iDesignoq jRulere Violation
io ei o qDVre - iDesignoq jRulere Verification
io ei o qGVre - iGeometryoq jViolation
io ei
io eAlli theothree qtermsre point itooq jthere same iprocess oofqchecking thatz theu ylayoute oiszx compliant with manufacture rules.
io ei o qre ioq jre a.Active-to-active ispacing
io ei o qre ioq jre b.Well-to-well ispacing
io ei o qre ioq jre c.Minimum ichannel olengthqof thez transistor .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n

io ei o qre ioq jre d.Minimum imetal owidth
io ei o qre ioq jre e.Metal-to-metal ispacing www.testbench.in

io ei o qre ioq jre f.Metal ifill odensity

io ei o qSVre - iScmaticoq jViolationre or iLVS o-qLayout versusz schematic
io ei o qThere other ipartoq jofre physical iverification oisqthe schematic/netlistz check.u yIte oiszx referred to as schematic verification (SV) or layout versus schematic (LVS).
io ei o qBothre terms idescribeoq jthere process iof ovalidatingqthat thez layoutu ymatchese othezx netlist/schematic.
io ei o q
io ei o qre ia.shorts
io ei o qre ib.opens
io ei o qre ic.componentoq jmissing
io ei o qre id.mismatchoq jofre component www.testbench.in

io ei o qre ie.propertyoq jerrors

(Q i6)o eTapei outo?

iTapeouto eisi theofinal qstepre of ichipoq jdesign.re It iis otheqtime atz whichu ythee odesignzx is fully qualified and ready for manufacturing. After the physical design is finished, the functionality of the netlist is verified, and the timing analysis is satisfied, the final layout, usually in GDSII (Gerber data stream information interchange) format, is sent to mask shop to generate photomask reticles. The resultant masks will be used to direct the manufacture of this chip.

(Q i7)o eNeedi ofoDFT q?re
Ans: .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n

After itheo emanufacturingi toocheck qwhetherre actual ibehavoroq jmatchesre the iexpected obehaviorqor not,z DFTu yise oused.


(Q i8)o eWhati willohappen qifre manufactured ichipoq jisre not iworking ofunctionalityq?

It ineedo etoi garbage.

(Q i9)o eYieldi ?

Ratio iino epercentagei ofonumber qofre working ichipsoq jtore total ino ochipsqin singlez u ywafer.


(Q i10)o eControllabilityi ?

Controllability imeasureso ethei abilityoto qcontrolre the iinternaloq jstatere of ithe ocircuitqthrough primaryz inputs.u yore oThezx ability to set or reset internal nodes from the primary inputs.

(Q i11)o eObservabilityi ? .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n


Observability imeasureso ethei abilityoto qobservere the iinternaloq jstatere of ithe ocircuitqthrough primaryz outputs.u yore oThezx ability to observe the value of an internal node at the primary outputs


(Q i12)o eHowi toodrive qtestre pattern i?

The itestso egenerallyi areodriven qbyre test iprogramsoq jthatre execute iin oAutomaticqTest Equipmentz (ATE).

Functional Verification Questions
Functional Verification Questions 2
Test Your Systemverilog Skills 1
Test Your Systemverilog Skills 2
Test Your Systemverilog Skills 3
Test Your Systemverilog Skills 4
Test Your Sva Skills
Test Your Verilog Skills 1
Test Your Verilog Skills 2
Test Your Verilog Skills 3
Test Your Verilog Skills 4
Test Your Verilog Skills 5
Test Your Verilog Skills 6
Test Your Verilog Skills 7
Test Your Verilog Skills 8
Test Your Verilog Skills 9
Test Your Verilog Skills 10
Test Your Verilog Skills 11
Test Your Verilog Skills 12
Test Your Verilog Skills 13
Test Your Verilog Skills 14
Test Your Verilog Skills 15
Test Your Verilog Skills 16
Test Your Verilog Skills 17
Test Your Specman Skills 1
Test Your Specman Skills 2
Test Your Specman Skills 3
Test Your Specman Skills 4
Test Your Sta Skills 1
Test Your Sta Skills 2
Test Your Sta Skills 3
Test Your Sta Skills 4
Test Your Sta Skills 5
Test Your Sta Skills 6
Test Your Sta Skills 7
Test Your Dft Skills 1
Test Your Dft Skills 2
Test Your Dft Skills 3
Test Your Dft Skills 4
Test Your Uvm Ovm Skills

Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!




copyright 2007-2017 :: all rights reserved www.testbench.in::Disclaimer