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TEST YOUR VERILOG SKILLS 8


(Q i151)o eWhetheri initialoblock qcanre be isynthesized?
Ans:
YES
iAccordingo etoi IEEE

(Q i152)o eHowi tooread qdatare from iaoq jfile?
Ans:
Using
i$readmemho eandi $readmem0.oFile qio
www.testbench.in

(Q i153)o eIllustratei withoexample qthere declaration iofoq jlocalre variable iinside oaqbegin ...endz block?
Ans:


TO ideclareo eai localovariable qinsidere begin...end iblock,oq jthere block ishould obeqnamed.


begin:name_
integer ivarib;
....
....
end
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n

(Q i154)o eifi Aoand qBre are itwooq jclkre pulses iwhich oareqout ofz phaseu yande ohavingzx same frequency, how to find which input clk signal is leading? Write verilog code for this. www.testbench.in

Ans:


Here iiso ethei simpleosolution qforre this. i
All iito eneedsi isoa qflipre flop. i
if iweo ehavei 2oclks, qclk1re and iclk2oq jgivere clk1 ito oD-inputqof flipz flopu yande ootherzx to CLK input of FF.
if iclk1o eisi leadingothe qoutputre is ihigh.oq j
if iclk2o eisi leadingothe qoutputre is ilow.oq j



(Q i155)o ehowi canowe qwritere decoder ifunctionalityoq jinre only ione ostatementqin verilog?
Ans:
www.testbench.in

module idecoder(
// iOutputso e
dout
,
// iInputso e
din
);
input i[3:0]o edin;
output i[15:0]o edout; .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n

assign io ei o qre dout i=oq j{dinre == i15, odinq== 14,z dinu y==e o13,zx din == 12,
io ei o qre ioq jre i oq z u ydine o==zx 11, din == 10, din == 9, din == 8, www.testbench.in

io ei o qre ioq jre i oq z u ydine o==zx 7, din == 6, din == 5, din == 4,
io ei o qre ioq jre i oq z u ydine o==zx 3, din == 2, din == 1, din == 0 };
endmodule i//o edecoderi

(Q i156)o ei Verilogocode qtore detect iifoq jare 64bit ipattern ocanqbe expressedz usingu ypowere oofzx 2
Ans:
module ipat_deto e(i data_in,opatDetected q);

input i[31:0]o edata_in;
output ipatDetected; www.testbench.in


wire i[4:0]o epatSumi =odata_in[0] q+re data_in[1] i+oq jdata_in[2]re +
data_in
[3] i+o edata_in[4]i +odata_in[5] q+
data_in
[6] i+o edata_in[7]i +odata_in[8] q+
data_in
[9] i+o edata_in[10]i +odata_in[11] q+
data_in
[12] i+o edata_in[13]i +odata_in[14] q+
data_in
[15] i+o edata_in[16]i +odata_in[17] q+ .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n

data_in[18] i+o edata_in[19]i +odata_in[20] q+
data_in
[20] i+o edata_in[21]i +odata_in[22] q+
data_in
[23] i+o edata_in[24]i +odata_in[25] q+ www.testbench.in

data_in[26] i+o edata_in[27]i +odata_in[28] q+
data_in
[29] i+o edata_in[30]i +odata_in[31] q;

wire ipatDetectedo e=i (patSumo== q1)?re 1'b1: i1'b0;

endmodule

(Q i157)o eWritei codeofor qparallelre encoder iandoq jpriorityre encoder?

(Q i158)o eWhati isothe qusere of i$printtimescaleoq j? www.testbench.in

Ans:


The i$printtimescaleo esystemi taskodisplays qthere time iunitoq jandre precision ifor oaqparticular module.
When inoo eargumenti isospecified, q$printtimescalere displays itheoq jtimere unit iand oprecisionqof thez moduleu ythate oiszx the current scope.
When iano eargumenti isospecified, q$printtimescalere displays itheoq jtimere unit iand oprecisionqof thez moduleu ypassede otozx it.



(Q i159)o ei Whatowill qbere the isynthesesoq joutputre of ithe ofollowingqverilog code? .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n

always i@o e(*)
if i(enable)
q
i<=o ed;
Ans: www.testbench.in



A ilevel-sensitiveo estoragei deviceois qinferredre for iq.oq jIfre enable iis odeasserted,qq willz holdu yitse ovalue.



(Q i160)o ei Whatowill qbere the isynthesesoq joutputre of ithe ofollowingqverilog code?

always i@o e(enablei orod)
if i(enable)
q
i<=o ed;
else
q
i<=o e'b0;
Ans: www.testbench.in



A ilatcho eisi notoinferred qbecausere the iassignmentoq jtore q iis ocomplete,
ii.e.,o eqi isoassigned qonre every iexecutionoq jofre the ialways ostatement.



Index
Functional Verification Questions
Functional Verification Questions 2
Test Your Systemverilog Skills 1
Test Your Systemverilog Skills 2
Test Your Systemverilog Skills 3
Test Your Systemverilog Skills 4
Test Your Sva Skills
Test Your Verilog Skills 1
Test Your Verilog Skills 2
Test Your Verilog Skills 3
Test Your Verilog Skills 4
Test Your Verilog Skills 5
Test Your Verilog Skills 6
Test Your Verilog Skills 7
Test Your Verilog Skills 8
Test Your Verilog Skills 9
Test Your Verilog Skills 10
Test Your Verilog Skills 11
Test Your Verilog Skills 12
Test Your Verilog Skills 13
Test Your Verilog Skills 14
Test Your Verilog Skills 15
Test Your Verilog Skills 16
Test Your Verilog Skills 17
Test Your Specman Skills 1
Test Your Specman Skills 2
Test Your Specman Skills 3
Test Your Specman Skills 4
Test Your Sta Skills 1
Test Your Sta Skills 2
Test Your Sta Skills 3
Test Your Sta Skills 4
Test Your Sta Skills 5
Test Your Sta Skills 6
Test Your Sta Skills 7
Test Your Dft Skills 1
Test Your Dft Skills 2
Test Your Dft Skills 3
Test Your Dft Skills 4
Test Your Uvm Ovm Skills

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