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TIPS


How To Avoid &Quot;Module Xxx Already Defined&Quot; Error




Sometimes compilation error "module xxx already defined" is tough to avoid when hundreds of files are there. Its hard to find where `include is including xxx file and how many times the file is given in compilation command.



EXAMPLE: xxx.v file

module xxx();

initial
$display(" MODULE ");

endmodule

EXAMPLE: yyy.v file
`include "xxx.v"
module yyy()

endmodule




Now compile with any of the comand.

compile_ur_command xxx.v yyy.v
compile_ur_command xxx.v yyy.v yyy.v

To avoid this problem, Just use compilation switches. In the following example initial macros XXX and YYY are not defined. When the compiler comes the xxx.v file first times, macro XXX is defined. Nedtime when the comes across xxx.v, as already the macro XXX is defined, it will neglect the module definition.



EXAMPLE: xxx.v file
`ifndef XXX
`define XXX
module xxx();

initial
$display(" MODULE ");

endmodule
`endif

EXAMPLE: yyy.v file
`include "xxx.v"
`ifndef YYY
`define YYY
module yyy()

endmodule
`endif



Now compile with any of the command.

compile_ur_command xxx.v yyy.v
compile_ur_command xxx.v yyy.v yyy.v

You will not see any compilation error.



Colourful Messages:





Look at the picture. Do you want to make your Linux terminal colorful like this, while you run your verilog code?

Copy the following code and simulate in batch mode in Linux. What you can see is colorful messages from verilog.



CODE:


module colour();

initial
begin
$write("%c[1;34m",27);
$display("*********** This is in blue ***********");
$write("%c[0m",27);

$display("%c[1;31m",27);
$display("*********** This is in red ***********");
$display("%c[0m",27);

$display("%c[4;33m",27);
$display("*********** This is in brown ***********");
$display("%c[0m",27);

$display("%c[5;34m",27);
$display("*********** This is in green ***********");
$display("%c[0m",27);

$display("%c[7;34m",27);
$display("*********** This is in Back ground color ***********");
$display("%c[0m",27);


end
endmodule




This works only in Linux or Unix terminals. To get required colors, ("%c[1;34m",27); should be used to print once. Ordinary messages following this messages continue to be the color specified.

Lets see how to get different colors and font format.
The message to be printed is ("%c[TYPE;COLOURm",27);.

TYPE specifies how the message should be?

1 set bold
2 set half-bright (simulated with color on a color display)
4 set underscore (simulated with color on a color display)
5 set blink
7 set reverse video

COLOR specifies the message color.

30 set black foreground
31 set red foreground
32 set green foreground
33 set brown foreground
34 set blue foreground
35 set magenta foreground
36 set cyan foreground
37 set white foreground

If you really want to use in your environment, use macros.



`define display_blue $write("%c[0m",27); $write("%c[1;34m",27); $display
`define display_red $write("%c[0m",27); $write("%c[1;31m",27); $display
`define display_green $write("%c[0m",27); $write("%c[1;32m",27); $display

Use the macros instead of $display().

EXAMPLE:
module color();

initial
begin
`display_blue(" ******** this is blue ********** ");
`display_red(" ******** this is red ********** ");
`display_green(" ******** this is green ********** ");

end

endmodule




Debugging Macros



Most tools don't support Debugging Macros. The compilation error information is not enough to find the exactly line where the bug is. In simulation/Compilation steps , the first step is Macro preprocessing. The macro preprocessing step performs textual substitutions of macros defined with `define statements, textual inclusion with `include statements, and conditional compilation by `ifdef and `ifndef statements.


EXAMPLE:

`define SUM(A,B) A + B ;

module example();

integer a,b,c;

initial
a = SUM(b,c);

endmodule



Run the above example and check where the error is.

The find the exact cause of error, simply use the C pre-processor.

Just use command



cpp file_name.v




NOTE: cpp cannot understand `define. Before using cpp, covert all `define to #define.

Output of the above code using cpp preprocessor is



RESULTS

# 1 "fine_name.v"
# 1 "<built-in>"
# 1 "<command line>"
# 1 "fine_name.v"

module example();

integer a,b,c;

initial
a = b + c ;;

endmodule




















































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Verilog Semaphore
Finding Testsenarious
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Terimination
Error Injuction
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Parameterised Macros
White Gray Black Box
Regression
Tips

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