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STIMULUS GENERATION




Verilog test benches range from simple descriptions signal values to descriptions that test vector files and high level controllable descriptions that use functions or tasks .There are many ways to create input test vectors to test DUT. Hardcoded value is simplest way of creating a test vectors. This I used to do when I was in schooling. As the number of inputs are less, this is comfortable to use.



EXAMPLE:
module Tb_mem();
reg clock;
reg read_write;
reg [31:0] data;
reg [31:0] address;

initial
begin
clock = 0;
forever
#10 clock = ~clock;
end

initial
begin
@(negedge clock) read_write = 1 ; data = 4;address = 1;
@(negedge clock) read_write = 1 ; data = 5;address = 2;
@(negedge clock) read_write = 1 ; data = 6;address = 3;
@(negedge clock) read_write = 1 ; data = 7;address = 4;
@(negedge clock) read_write = 1 ; data = 8;address = 5;
$finish;
end

initial
$monitor($time,"read_write = %d ; data = %d ; address = %d;",read_write,data,address);

endmodule

RESULT:

20read_write = 1 ; data = 4 ; address = 1;
40read_write = 1 ; data = 5 ; address = 2;
60read_write = 1 ; data = 6 ; address = 3;
80read_write = 1 ; data = 7 ; address = 4;




Another way of getting the Stimulus is get the vectors from an external file. The external vector file is generally formatted so that each value in the file represents either a specific input pattern .Verilog HDL contains the $readmemb or $readmemh system tasks to do the file read if the file data is formatted in a specific way using either binary or hexadecimal data.

Fallowing example illustrates how to initialize a memory array from data stored as hexadecimal values in a data file, Simulate this file directly to see the results.
Note: The data file must reside in the same directory as the .v file for the module in this example.



EXAMPLE: verilog file
module readmemh_demo;

reg [31:0] Mem [0:11];

initial $readmemh("data.txt",Mem);

integer k;

initial begin
#10;
$display("Contents of Mem after reading data file:");
for (k=0; k<6; k=k+1) $display("%d:%h",k,Mem[k]);
end

endmodule

EXAMPLE: data.txt file
234ac
23ca5
b3c34
23a4a
234ca
b3234

RESULT:

0:000234ac
1:00023ca5
2:000b3c34
3:00023a4a
4:000234ca
5:000b3234




With the above approach,its not possible to list all the combinations manually if the number of vectors get increases.


Index
Introduction
Linear Tb
File Io Tb
State Machine Based Tb
Task Based Tb
Self Checking Testbench
Verification Flow
Clock Generator
Simulation
Incremental Compilation
Store And Restore
Event Cycle Simulation
Time Scale And Precision
Stimulus Generation
System Function Random A Myth
Race Condition
Checker
Task And Function
Process Control
Disableing The Block
Watchdog
Compilation N Simulation Switchs
Debugging
About Code Coverage
Testing Stratigies
File Handling
Verilog Semaphore
Finding Testsenarious
Handling Testcase Files
Terimination
Error Injuction
Register Verification
Parameterised Macros
White Gray Black Box
Regression
Tips

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