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STATE MACHINE BASED TB




By definition, a stat machine TestBench used state machine to generate input vector and drive it to the I/O ports of the design. One testbench can have multiple state machines each handling a different functionality. To achieve the quality of verification required by today's complex designs, testbench must be robust. State machine based verification cannot support todays verification needs. A state machine based testbench is hardly seen nowadays.


always@(posedge clk)
case(state)
READ : if(i < No_of_reads)
begin
read_write = 0;
address = $random;
i=i+1;
end
else
$finish
WRITE : if(j < no_of_writes)
begin
read_write = 1;
address = $random;
data = $random;
j=j+1;
end
else
state = READ ;
endcase




Now lets see how to develop our scenarios:
Only 10 write operations,


initial
begin
No_of_reads = 0;
No_of_writes = 10;
end



Only 10 read operations,


initial
begin
No_of_reads = 10;
No_of_writes = 0;
end


With the above style of testbench, the controllability is less and hard to change the code to add new features like to convert the above code to alternate read and write operation, its very difficult.


Index
Introduction
Linear Tb
File Io Tb
State Machine Based Tb
Task Based Tb
Self Checking Testbench
Verification Flow
Clock Generator
Simulation
Incremental Compilation
Store And Restore
Event Cycle Simulation
Time Scale And Precision
Stimulus Generation
System Function Random A Myth
Race Condition
Checker
Task And Function
Process Control
Disableing The Block
Watchdog
Compilation N Simulation Switchs
Debugging
About Code Coverage
Testing Stratigies
File Handling
Verilog Semaphore
Finding Testsenarious
Handling Testcase Files
Terimination
Error Injuction
Register Verification
Parameterised Macros
White Gray Black Box
Regression
Tips

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