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TERIMINATION




Simulation should terminate after all the required operations are done. Recommended way to exit simulation is using a task. This termination task contains some messages about the activities done and $finish. This task should be called after collecting all the responses from DUT, then analyzing them only. If the simulation time is long and if there is bug in DUT, you can stop simulation at that time itself. This saves lot of time. Otherwise, even after the testbench found error, it will simulate till the end of the process or it may get hanged and waste your time and costly licenses.

Sometimes, you are not just interested to terminate the simulation for known unfixed bugs. Then there should be a controllable way not to stop the simulation even after the error was found.



EXAMPLE:

task teriminate();
begin
if(no_of_errors == 0)
$display(" *********TEST PASSED ***********");
else
$display(" *********TEST FAILED ***********");

#10 $display(" SIMULATION TERMINATION at %d",$time);
$finish;
end
endtask

always@(error)
begin
no_of_errors = num_of_errors +1 ;

`ifndef CONTINUE_ON_ERROR
terminate();
`endif
end




If you know already a well known bug is there and it is giving 2 error counts. Its better to stop the simulation after 2 errors. From command line just give +define+NO_FO_ERR=2, simulation terminates after 3 errors.



EXAMPLE:
always@(error)
begin
no_of_errors = num_of_errors +1 ;

`ifndef CONTINUE_ON_ERROR
`ifndef NO_OF_ERR
`define NO_OF_ERR 0
`endif
if(`NO_OF_ERR < no_of_erros)
terminate();
`endif
end
Index
Introduction
Linear Tb
File Io Tb
State Machine Based Tb
Task Based Tb
Self Checking Testbench
Verification Flow
Clock Generator
Simulation
Incremental Compilation
Store And Restore
Event Cycle Simulation
Time Scale And Precision
Stimulus Generation
System Function Random A Myth
Race Condition
Checker
Task And Function
Process Control
Disableing The Block
Watchdog
Compilation N Simulation Switchs
Debugging
About Code Coverage
Testing Stratigies
File Handling
Verilog Semaphore
Finding Testsenarious
Handling Testcase Files
Terimination
Error Injuction
Register Verification
Parameterised Macros
White Gray Black Box
Regression
Tips

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