Simulation Steps:

Simulation is defined as the process of creating a model (i.e., an abstract representation) of a system in order to identify and understand those factors which control the system and/or to predict (forecast) the future behavior of the system. The simulation model need not reflect any understanding of the underlying technology, and the simulator need not know that the design is intended for any specific technology.

The underlying purpose of simulation is to shed light on the underlying mechanisms that control the behavior of a system. More practically, simulation can be used to predict (forecast) the future behavior of a system, and determine what you can do to influence that future behavior. That is, simulation can be used to predict the way in which the system will evolve and respond to its surroundings, so that you can identify any necessary changes that will help make the system perform the way that you want it to.

Simulation Eliminates the time-consuming need for constant physical prototyping. Simulation should be performed during ALL stages of ASIC design.

Macro Preprocessing:

The macro preprocessing step performs textual substitutions of macros defined with `define statements, textual inclusion with `include statements, and conditional compilation by `ifdef and `ifndef statements.

Compilation (Analyzer)

Checks source code to check syntax and semantic rules. If a syntax or semantic error occurs, then the compiler gives error message. If there are no errors , compilation produces an internal representation for each HDL design unit.


The elaboration process constructs a design hierarchy based on the instantiation and configuration information in the design, establishes signal connectivity . Memory storage is allocated for the required signals. The elaboration process creates a hierarchy of module instances that ends with primitive gates and statements.


Some tools support optimization at this level. This is optional step.

Initialization :

Initial values preset in the declarations statement are assigned to signals / variables.


Every process is executed until it suspends. Signal values are updated only after the process suspends. Simulator accepts simulation commands like (run, assign, watch), which control the simulation of the system and specify the desired simulator output. Simulation ends when all signals have been updated and new values have been assigned to signals. This design hierarchy is stored in a simulation snapshot. The snapshot is the representation of your design that the simulator uses to run the simulation.

Simulation Process :

When Simulation time is incremented, On receiving Simulation commands, a signal is updated. All processes sensitive to that signal are placed on a ¿Process Execution¿ queue. Each resumed process is executed until it suspends. Effects of the logic changes that have occurred as a result of process execution are evaluated. Simulation time is set to the next event in queue, or halted if simulation time is exhausted.

Linear Tb
File Io Tb
State Machine Based Tb
Task Based Tb
Self Checking Testbench
Verification Flow
Clock Generator
Incremental Compilation
Store And Restore
Event Cycle Simulation
Time Scale And Precision
Stimulus Generation
System Function Random A Myth
Race Condition
Task And Function
Process Control
Disableing The Block
Compilation N Simulation Switchs
About Code Coverage
Testing Stratigies
File Handling
Verilog Semaphore
Finding Testsenarious
Handling Testcase Files
Error Injuction
Register Verification
Parameterised Macros
White Gray Black Box

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