The disable statement stops the execution of a labeled block and skips to the end of the block. Blocks can be named by adding : block_name after the keyword begin or fork. Named block can only be disabled using disable statement.
This example illustrates how a block disables itself.
EXAMPLE: begin : block_name
rega = regb;
regc = rega; // this assignment will never execute
This example shows the disable statement being used as an early return from a task. However, a task disabling itself using a disable statement is not a short-hand for the
return statement found in programming languages.
EXAMPLE: task abc();
begin : name
if( something happened)
Verilog does not have a goto, but the effect of a forward goto can be acheived as shown:
EXAMPLE: begin: name
Execution will continue with the next statement after the end statement when the disable is executed.
The break statement as in C can be emulated with disable as shown in the following example:
EXAMPLE: begin: break for (i=0; i<16; i=i+1) begin ...
The continue statement in C causes the current iteration of a loop to be terminated, with execution continuing with the next iteration. To do the same thing in Verilog, you can do this:
EXAMPLE: for (i=0; i<16; i=i+1) begin: name