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ERROR INJUCTION




To verify error detection, reporting, and recovery features of the DUT, an error injection mechanism must be in place in testbench to generate error scenarios. The objective is to ensure that the errors are handled correctly. This is accomplished by introducing internal monitoring mechanisms. The simulation environment integrates a structure to randomly set the errors and verify that each error condition is handled properly.

Errors can be classified in to following categories:


Value Errors



The specification says that packet length should be greater than 64 and less than 1518. Testbench should be able to generate packets of length less than 64 and greater than 1518 and verify how the DUT is handling these. Testbench should also monitor that DUT is not generating any packets violating this rule.


Temporal Errors



Errors like acknowledgement should come after 4 cycles of request.



Interface Error



Sometimes interfaces have invalid pins or error pins to inform to DUT that the some malfunction happened. Generate scenarios to test whether the DUT is properly responding to these signals.



Sequence Errors



To test protocols which define sequence of operations, generate sequence which violates the rule and check the DUT.


Index
Introduction
Linear Tb
File Io Tb
State Machine Based Tb
Task Based Tb
Self Checking Testbench
Verification Flow
Clock Generator
Simulation
Incremental Compilation
Store And Restore
Event Cycle Simulation
Time Scale And Precision
Stimulus Generation
System Function Random A Myth
Race Condition
Checker
Task And Function
Process Control
Disableing The Block
Watchdog
Compilation N Simulation Switchs
Debugging
About Code Coverage
Testing Stratigies
File Handling
Verilog Semaphore
Finding Testsenarious
Handling Testcase Files
Terimination
Error Injuction
Register Verification
Parameterised Macros
White Gray Black Box
Regression
Tips

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