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Tutorials



FILE IO TB


File I/O Based Testbench



Another way of getting the Stimulus is get the vectors from an external file. The external vector file is generally formatted so that each value in the file represents either a specific input pattern .Verilog HDL contains the $readmemb or $readmemh system tasks to do the file read if the file data is formatted in a specific way using either binary or hexadecimal data. TestBench is like just an interface between external vector source and DUT. Sometimes outputs are also to written to external files. For example, to verify a a dsp algorithm implemented as DUT, get the input vectors from matlab tool and send the outputs to a file and then compare the outputs of the matlab for the same algorithm.

Fallowing example illustrates how to initialize a memory array from data stored as hexadecimal values in a data file, Simulate this file directly to see the results.
Note: The data file must reside in the same directory as the .v file for the module in this example.



EXAMPLE: verilog file
module readmemh_demo;

reg [31:0] Mem [0:11];

initial $readmemh("data.txt",Mem);

integer k;
initial begin
#10;
$display("Contents of Mem after reading data file:");
for (k=0; k<6; k=k+1) $display("%d:%h",k,Mem[k]);
end

endmodule

EXAMPLE: data.txt file
234ac
23ca5
b3c34
23a4a
234ca
b3234

RESULT:

0:000234ac
1:00023ca5
2:000b3c34
3:00023a4a
4:000234ca
5:000b3234




Reading or writing to files during simulation is costly to performance, because the simulator must halt and wait while the OS completes each transaction with the file system. One way to improve performance is to replace ASCII vector files with a constant table in HDL itself. Do this using Perl script.



module readmemh_demo;

reg [31:0] Mem [0:11];

`include "data.v"

integer k;
initial begin
#10;
$display("Contents of Mem after reading data file:");
for (k=0; k<6; k=k+1) $display("%d:%h",k,Mem[k]);
end

endmodule

EXAMPLE: data.v file
initial
begin
Mem[0] = 32'h234ac;
Mem[1] = 32'h23ca5;
Mem[2] = 32'hb3c34;
Mem[3] = 32'h23a4a;
Mem[4] = 32'h234ca;
Mem[5] = 32'hb3234;
end

RESULT:

0:000234ac
1:00023ca5
2:000b3c34
3:00023a4a
4:000234ca
5:000b3234

Index
Introduction
Linear Tb
File Io Tb
State Machine Based Tb
Task Based Tb
Self Checking Testbench
Verification Flow
Clock Generator
Simulation
Incremental Compilation
Store And Restore
Event Cycle Simulation
Time Scale And Precision
Stimulus Generation
System Function Random A Myth
Race Condition
Checker
Task And Function
Process Control
Disableing The Block
Watchdog
Compilation N Simulation Switchs
Debugging
About Code Coverage
Testing Stratigies
File Handling
Verilog Semaphore
Finding Testsenarious
Handling Testcase Files
Terimination
Error Injuction
Register Verification
Parameterised Macros
White Gray Black Box
Regression
Tips

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