A watchdog timer is a piece of code, that can take appropriate action when it judges that a system is no longer executing the correct sequence of code. In this topic ,I will discuss exactly the sort of scenarios a watch dog can detect, and the decision that must be made by watchdog. Generally speaking, a watchdog timer is based on a counter that counts down from some initial value to zero. If the counter reaches, then the appropriate action is take. If the required functionality is archived, watchdog can be disabled.
In software world, in watchdog articles you will see various terms like strobing, stroking etc. In this topic I will use more visual metaphor of man kicking the dog periodically-with apologies to animal lovers. If the man stops kicking the dog, the dog will take advantage of hesitation and bite the man. The man has to take a proper decision for the dog bite. The process of restarting the watchdog timer's counter is sometimes called "kicking the dog.".Bugs in DUT can cause the testbench to hang, if they lead to an infinite loop and creating a deadlock condition. A properly designed watchdog should catch events that hang the testbench.
Once your watchdog has bitten ,you have to decide what action to be taken. The testbench will usually assert the error message, other actions are also possible like directly stop simulation or just give a warning in performance tests.
In the following example, I have taken a DUT model so its easy to understand than a RTL to demonstrate watchdog.
DUT PROTOCOL:
DUT has 3 signals.Clock a,b;
output b should be 1 within 4 clock cycles after output a became 1.
There are two scenarios I generated in DUT. one is following the above protocol and the other violated the above rule. The testbench watchdog shows how it caught there two scenarios.
initial begin repeat(10)@(posedge clock) a = 0;b = 0;
@(posedge clock) a = 1;b = 0;
@(posedge clock) a = 0;b = 0;
@(posedge clock) a = 0;b = 0;
@(posedge clock) a = 0;b = 1;
repeat(10)@(posedge clock) a = 0;b = 0;
@(posedge clock) a = 1;b = 0;
@(posedge clock) a = 0;b = 0;
end endmodule
module TB();
wire aa,bb;
reg clk;
DUT dut(clk,aa,bb);
always #5 clk = ~clk;
initial #400 $finish;
initial begin clk = 0;
$display(" TESTBENCH STARTED");
wait(aa == 1) ;
watchdog();
wait( aa == 1);
watchdog();
end
task watchdog();
begin $display(" WATCHDOG : started at %0d ",$time);
fork : watch_dog
begin wait( bb == 1);
$display(" bb is asserted time:%0d",$time);
$display(" KICKING THE WATCHDOG ");
disable watch_dog;
end begin repeat(4)@(negedge clk);
$display(" bb is not asserted time:%0d",$time);
$display(" WARNING::WATCHDOG BITED ");
disable watch_dog;
end join end endtask
endmodule
RESULTS:
TESTBENCH STARTED WATCHDOG : started at 105 bb is asserted time:135 KICKING THE WATCHDOG WATCHDOG : started at 245 bb is not asserted time:280 WARNING::WATCHDOG BITED
Statement " disable watch_dog " is the trick hear. If that statement is not there, the statement " wait(b == 1) " is waiting and the simulation goes hang. This watchdog is just giving a warning about bite. You can also assert a ERROR message and call $finish to stop simulation.