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VERIFICATION FLOW




Verification of a design usually follows the flow synopsis below.


Planning:



After the preliminary design specification is completed, the first verification phase is started Verification planning.

Verification planning consists, following main tasks.

1) Feature extraction from design specification.
2) Listing out Testcases.
3) Verification Environment Architecture plan.



Feature Extraction:



Extract all the features of the DUT from the design specification.
Mainly the features are configuration, Interface protocol, data processing protocol and status communication.
Categorizing all this features according to where these features are verified.
What are the features covered by random stimulus generation?
What are the features verifiable by writing separate test cases?
What features assertions can catch?
What features the coverage module contains?



Verification Environment Architecture Plan:



Verification plan contains the structure of the Verification environment. Based on the project requirements, following points are considered while Architecture is built.
Reusability, Is it a verification IP. What blocks the verification language can support.
Controllability of the stimulus generation etc.

Next phase is to build the Verification environment.
Final phase is to verify the DUT using the environment built.




Index
Introduction
Linear Tb
File Io Tb
State Machine Based Tb
Task Based Tb
Self Checking Testbench
Verification Flow
Clock Generator
Simulation
Incremental Compilation
Store And Restore
Event Cycle Simulation
Time Scale And Precision
Stimulus Generation
System Function Random A Myth
Race Condition
Checker
Task And Function
Process Control
Disableing The Block
Watchdog
Compilation N Simulation Switchs
Debugging
About Code Coverage
Testing Stratigies
File Handling
Verilog Semaphore
Finding Testsenarious
Handling Testcase Files
Terimination
Error Injuction
Register Verification
Parameterised Macros
White Gray Black Box
Regression
Tips

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