All procedures in the Verilog HDL are specified within one of the following four statements:
-- initial construct
-- always construct
-- Task
-- Function

The initial and always constructs are enabled at the beginning of a simulation. The initial construct shall execute only once and its activity shall cease when the statement has finished. In contrast, the always construct shall execute repeatedly. Its activity shall cease only when the simulation is terminated. There shall be no implied order of execution between initial and always constructs. The initial constructs need not be scheduled and executed before the always constructs. There shall be no limit to the number of initial and always constructs that can be defined in a module


An initial block consists of a statement or a group of statements enclosed in begin... end or a signle statement , which will be executed only once at simulation time 0. If there is more than one block they execute concurrently and independently. The initial block is normally used for initialisation, monitoring, generating wave forms (eg, clock pulses) and processes which are executed once in a simulation. An example of initialisation and wave generation is given below

clock = 1'b0; // variable initialization

begin // multiple statements have to be grouped
alpha = 0;
#10 alpha = 1; // waveform generation
#20 alpha = 0;
#5 alpha = 1;
#7 alpha = 0;
#10 alpha = 1;
#20 alpha = 0;


An always block is similar to the initial block, but the statements inside an always block will repeated continuously, in a looping fashion, until stopped by $finish or $stop.

NOTE: the $finish command actually terminates the simulation where as $stop. merely pauses it and awaits further instructions. Thus $finish is the preferred command unless you are using an interactive version of the simulator.

One way to simulate a clock pulse is shown in the example below. Note, this is not the best way to simulate a clock. See the section on the forever loop for a better method.

module pulse;

reg clock;

initial clock = 1'b0; // start the clock at 0
always #10 clock = ~clock; // toggle every 10 time units
initial #5000 $finish // end the simulation after 5000 time units


Tasks and functions can bu used to in much the same manner but there are some important differences that must be noted.


A function is unable to enable a task however functions can enable other functions.
A function will carry out its required duty in zero simulation time.
Within a function, no event, delay or timing control statements are permitted.
In the invocation of a function their must be at least one argument to be passed.
Functions will only return a single value and can not use either output or inout statements.
Functions are synthesysable.
Disable statements canot be used.
Function canot have numblocking statements.


module function_calling(a, b,c);

input a, b ;
output c;
wire c;

function myfunction;
input a, b;
myfunction = (a+b);

assign c = myfunction (a,b);



Tasks are capable of enabling a function as well as enabling other versions of a Task
Tasks also run with a zero simulation however they can if required be executed in a non zero simulation time.
Tasks are allowed to contain any of these statements.
A task is allowed to use zero or more arguments which are of type output, input or inout.
A Task is unable to return a value but has the facility to pass multiple values via the output and inout statements.
Tasks are not synthesisable.
Disable statements can be used.

module traffic_lights;
reg clock, red, amber, green;
parameter on = 1, off = 0, red_tics = 350,
amber_tics = 30, green_tics = 200;
// initialize colors.
initial red = off;
initial amber =

Data Types
Control Constructs
Procedural Timing Controls
Block Statements
Structured Procedures

Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!




copyright 2007-2017 :: all rights reserved www.testbench.in::Disclaimer