A module in Verilog is used to define a circuit or a sub circuit. The module is the fundamental circuit building block in Verilog. Modules have the following structure: (keywords in bold). Note that the module declaration ends with a semicolon but the keyword endmodule does not.
Ports in Verilog can be of type input, output¸ or inout. The module ports are given in the port name list and are declared in the beginning of the module. Here is a sample module with input and output ports.
The port names input and output default to type wire. Either can be a vector and the output variables can be of redeclared to type reg. The output and input variables in a module are typically names for the output and input pins on the implementation chip.
a signal is represented by either a net type or a variable type in Verilog. The net type represents a circuit node and these can be of several types. The two net types most often used are wire and tri. Type nets do not have to be declared in Verilog since Verilog assumes that all signals are nets unless they are declared otherwise. Variables are either of type reg or integer. Integers are always 32-bits where the reg type of variables may be of any length. Typically we use integers as loop counters and reg variables for all other variables. The generic form for representing a signal in Verilog is:
CODE: type[range] signal_name
The range is omitted for scalar variables but used for vectors.
The net types are typically used for input signals and for intermediate signals within combinational logic. Variables are used for sequential circuits or for outputs which are assigned a value within a sequential always block.
EXAMPLEs: wire w; //w is a single net of type wire
wire[2:0] wVect; //Declares wVect, wVect, wVect
tri[7:0] bus //An 8-bit tri state bus
integer i; //i is a 32-bit integer used for loop control
reg r; //r is a 1-bit register
reg[7:0] buf; //buf is an 8-bit register
reg[3:0] r1, r2 //r1 and r2 are both 4-bit registers