The Verilog® Hardware Description Language (Verilog HDL) became an IEEE standard in 1995 as IEEE Std 1364-1995. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware.
Verilog contains a rich set of built-in primitives, including logic gates, user-definable primitives, switches,
and wired logic. It also has device pin-to-pin delays and timing checks.
The Verilog language is extensible via the Programming Language Interface (PLI) and the Verilog Procedural
Interface (VPI) routines.