|HOME |ABOUT |ARTICLES |ACK |FEEDBACK |TOC |LINKS |BLOG |JOBS |


Tutorials



ASSIGNMENTS



The assignment is the basic mechanism for placing values into nets and variables. There are two basic forms of assignments:
-- The continuous assignment, which assigns values to nets
-- The procedural assignment, which assigns values to variables



Legal left-hand side forms in assignment statements
-----------------------------------------------------------------
Statement type            Left-hand side (LHS)
-----------------------------------------------------------------
Continuous assignment     Net (vector or scalar)
                          Constant bit select of a vector net
                          Constant part select of a vector net
                          Constant indexed part select of a vector net
                          Concatenation of any of the above four LHS
-----------------------------------------------------------------
Procedural assignment     Variables (vector or scalar)
                          Bit-select of a vector reg, integer, or time variable
                          Constant part select of a vector reg, 
                                   integer, or time variable
                          Memory word
                          Indexed part select of a vector reg, 
                                  integer, or time variable
                          Concatenation of regs; bit or part selects of regs

-----------------------------------------------------------------


The following is an example of the use of a continuous assignment to model a 4-bit adder.


EXAMPLE:
module adder (sum_out, carry_out, carry_in, ina, inb);
output [3:0] sum_out;
output carry_out;
input [3:0] ina, inb;
input carry_in;
wire carry_out, carry_in;
wire [3:0] sum_out, ina, inb;
assign {carry_out, sum_out} = ina + inb + carry_in;
endmodule

The following is an example of the use of a Procedural assignment to model a 4-bit adder.
EXAMPLE:
module adder (sum_out, carry_out, carry_in, ina, inb);
output [3:0] sum_out;
output carry_out;
input [3:0] ina, inb;
input carry_in;
reg carry_out;
wire carry_in;
reg [3:0] sum_out;
wire [3:0] ina, inb;

always@(ina or inb or carry_in)
{carry_out, sum_out} = ina + inb + carry_in;

endmodule

Blocking Procedural Assignments



A blocking procedural assignment statement shall be executed before the execution of the statements that follow it in a sequential block. A blocking procedural assignment statement shall not prevent the execution of statements that follow it in a parallel block .



EXAMPLE:
rega = 0;
rega[3] = 1; // a bit-select
rega[3:5] = 7; // a part-select
mema[address] = 8'hff; // assignment to a mem element
{carry, acc} = rega + regb; // a concatenation

The Nonblocking Procedural Assignment



The nonblocking procedural assignment allows assignment scheduling without blocking the procedural flow. The nonblocking procedural assignment statement can be used whenever several variable assignments within the same time step can be made without regard to order or dependence upon each other.



EXAMPLE:

module evaluates2 (out);
output out;
reg a, b, c;
initial begin
a = 0;
b = 1;
c = 0;
end
always c = #5 ~c;
always @(posedge c) begin
a <= b; // evaluates, schedules,
b <= a; // and executes in two steps
end
endmodule

Procedural Continuous Assignments



The procedural continuous assignments (using keywords assign and force) are procedural statements that allow expressions to be driven continuously onto variables or nets.

The left-hand side of the assignment in the assign statement shall be a variable reference or a concatenation of variables. It shall not be a memory word (array reference) or a bit-select or a part-select of a variable. In contrast, the left-hand side of the assignment in the force statement can be a variable reference or a net reference. It can be a concatenation of any of the above. Bit-selects and part-selects of vector variables are not allowed.



Assign And Deassign Procedural Statements



The assign procedural continuous assignment statement shall override all procedural assignments to a variable. The deassign procedural statement shall end a procedural continuous assignment to a variable. The value of the variable shall remain the same until the reg is assigned a new value through a procedural assignment or a procedural continuous assignment.



EXAMPLE:
module dff (q, d, clear, preset, clock);
output q;
input d, clear, preset, clock;
reg q;
always @(clear or preset)
if (!clear)
assign q = 0;
else if (!preset)
assign q = 1;
else
deassign q;
always @(posedge clock)
q = d;
endmodule

Force And Release Procedural Statements



Another form of procedural continuous assignment is provided by the force and release procedural statements. These statements have a similar effect to the assign-deassign pair, but a force can be applied to nets as well as to variables. The left-hand side of the assignment can be a variable, a net, a constant bit-select of a vector net, a part-select of a vector net, or a concatenation. It cannot be a memory word (array reference) or a bit-select or a part-select of a vector variable.

A force statement to a variable shall override a procedural assignment or procedural continuous assignment that takes place on the variable until a release procedural statement is executed on the variable. After the release procedural statement is executed, the variable shall not immediately change value (as would a net that is assigned with a procedural continuous assignment). The value specified in the force statement shall be maintained in the variable until the next procedural assignment takes place, except in the case where a procedural continuous assignment is active on the variable.

A force procedural statement on a net overrides all drivers of the net gate outputs, module outputs, and continuous assignments until a release procedural statement is executed on the net. Releasing a variable that currently has an active procedural continuous assignment shall re-establish that assignment.



EXAMPLE:
module test;
reg a, b, c, d;
wire e;
and and1 (e, a, b, c);
initial begin
$monitor("%d d=%b,e=%b", $stime, d, e);
assign d = a & b & c;
a = 1;
b = 0;
c = 1;
#10;
force d = (a | b | c);
force e = (a | b | c);
#10 $stop;
release d;
release e;
#10 $finish;
end
endmodule
Results:
0 d=0,e=0
10 d=1,e=1
20 d=0,e=0


Delays



Delays are not synthesysable. In a delayed assignment Dt time units pass before the statement is executed and the left-hand assignment is made. With intra-assignment delay, the right side is evaluated immediately but there is a delay of Dt before the result is place in the left hand assignment. If another procedure changes a right-hand side signal during Dt, it does not effect the output. Delays are not supported by synthesis tools.



Inter Assignmnet Delay .



This is the most common delay used - sometimes also referred to as inter-assignment delay control.


EXAMPLE:

#10 q = x + y;


It simply waits for the appropriate number of timesteps before executing the command.


Intra-Assignment Delay Control



With this kind of delay, the value of x + y is stored at the time that the assignment is executed, but this value is not assigned to q until after the delay period, regardless of whether or not x or y have changed during that time.


EXAMPLE:

q = #10 x + y;

Index
Introduction
Syntax
Data Types
Operators
Assignments
Control Constructs
Procedural Timing Controls
Structure
Block Statements
Structured Procedures

Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!





<< PREVIOUS PAGE

TOP

NEXT PAGE >>

copyright 2007-2017 :: all rights reserved www.testbench.in::Disclaimer