| |||
|---|---|---|---|
|
|
||
CONTROL CONSTRUCTS
Verilog HDL has a rich collection of control statements which can used in the procedural sections of code, i. e., within an initial or always block. Most of them will be familiar to the programmer of traditional programming languages like C. The main difference is instead of C's { } brackets, Verilog HDL uses begin and end. In Verilog, the { } brackets are used for concatenation of bit strings. Since most users are familiar with C, the following subsections typically show only an example of each construct.
If And If Else Statements
The conditional statement (or if-else statement) is used to make a decision as to whether a statement is executed or not.
EXAMPLE:
if (A == 4)
begin
B = 2;
end
else
begin
B = 4;
end
Case
The case statement is a multiway decision statement that tests whether an expression matches one of a number of other expressions and branches accordingly.
case (<expression>)
<value1>: <statement>
<value2>: <statement>
default: <statement>
endcase
The following example checks a 1-bit signal for its value.
EXAMPLE:
case (sig)
1'bz: $display("Signal is floating");
1'bx: $display("Signal is unknown");
default: $display("Signal is %b", sig);
endcase
Forever
Forever Continuously executes a statement or block till the end of simulation.
EXAMPLE:
initial
clock =0;
forever
#10 clock = ~clock;
end
Repeat
Executes a statement a fixed number of times. If the expression evaluates to unknown or high impedance, it shall be treated as zero, and no statement shall be executed.
EXAMPLE:
parameter size = 8, longsize = 16;
reg [size:1] opa, opb;
reg [longsize:1] result;
begin : mult
reg [longsize:1] shift_opa, shift_opb;
shift_opa = opa;
shift_opb = opb;
result = 0;
repeat (size) begin
if (shift_opb[1])
result = result + shift_opa;
shift_opa = shift_opa << 1;
shift_opb = shift_opb >> 1;
end
end
While
Executes a statement until an expression becomes false. If the expression starts out false, the statement shall not be executed at all.
EXAMPLE:
begin : count1s
reg [7:0] tempreg;
count = 0;
tempreg = rega;
while (tempreg) begin
if (tempreg[0])
count = count + 1;
tempreg = tempreg >> 1;
end
end
For
Controls execution of its associated statement(s) by a three-step process, as follows:
a) Executes an assignment normally used to initialize a variable that controls the number of loops executed.
b) Evaluates an expression if the result is zero, the for-loop shall exit, and if it is not zero, the for-loop shall execute its associated statement(s) and then perform step c. If the expression evaluates to an unknown or high-impedance value, it shall be treated as zero.
c) Executes an assignment normally used to modify the value of the loop-control variable, then repeats step b.
EXAMPLE:
begin
initial_assignment;
while (condition) begin
statement
step_assignment;
end
end
Verilog HDL has a rich collection of control statements which can used in the procedural sections of code, i. e., within an initial or always block. Most of them will be familiar to the programmer of traditional programming languages like C. The main difference is instead of C's { } brackets, Verilog HDL uses begin and end. In Verilog, the { } brackets are used for concatenation of bit strings. Since most users are familiar with C, the following subsections typically show only an example of each construct.
If And If Else Statements
The conditional statement (or if-else statement) is used to make a decision as to whether a statement is executed or not.
EXAMPLE:
if (A == 4)
begin
B = 2;
end
else
begin
B = 4;
end
Case
The case statement is a multiway decision statement that tests whether an expression matches one of a number of other expressions and branches accordingly.
case (<expression>)
<value1>: <statement>
<value2>: <statement>
default: <statement>
endcase
The following example checks a 1-bit signal for its value.
EXAMPLE:
case (sig)
1'bz: $display("Signal is floating");
1'bx: $display("Signal is unknown");
default: $display("Signal is %b", sig);
endcase
Forever
Forever Continuously executes a statement or block till the end of simulation.
EXAMPLE:
initial
clock =0;
forever
#10 clock = ~clock;
end
Repeat
Executes a statement a fixed number of times. If the expression evaluates to unknown or high impedance, it shall be treated as zero, and no statement shall be executed.
EXAMPLE:
parameter size = 8, longsize = 16;
reg [size:1] opa, opb;
reg [longsize:1] result;
begin : mult
reg [longsize:1] shift_opa, shift_opb;
shift_opa = opa;
shift_opb = opb;
result = 0;
repeat (size) begin
if (shift_opb[1])
result = result + shift_opa;
shift_opa = shift_opa << 1;
shift_opb = shift_opb >> 1;
end
end
While
Executes a statement until an expression becomes false. If the expression starts out false, the statement shall not be executed at all.
EXAMPLE:
begin : count1s
reg [7:0] tempreg;
count = 0;
tempreg = rega;
while (tempreg) begin
if (tempreg[0])
count = count + 1;
tempreg = tempreg >> 1;
end
end
For
Controls execution of its associated statement(s) by a three-step process, as follows:
a) Executes an assignment normally used to initialize a variable that controls the number of loops executed.
b) Evaluates an expression if the result is zero, the for-loop shall exit, and if it is not zero, the for-loop shall execute its associated statement(s) and then perform step c. If the expression evaluates to an unknown or high-impedance value, it shall be treated as zero.
c) Executes an assignment normally used to modify the value of the loop-control variable, then repeats step b.
EXAMPLE:
begin
initial_assignment;
while (condition) begin
statement
step_assignment;
end
end
Index
Introduction
Syntax
Data Types
Operators
Assignments
Control Constructs
Procedural Timing Controls
Structure
Block Statements
Structured Procedures
Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!
Introduction
Syntax
Data Types
Operators
Assignments
Control Constructs
Procedural Timing Controls
Structure
Block Statements
Structured Procedures
Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!