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SYNTAX
Comments : Verilog comments are the same as in C++. Use // for a single line comment or /* */ for a multiline comment.
Punctuation : white spaces are ignored in Verilog. A semicolon is used to indicate the end of a command line and commas are typically used to separate elements in a list. Like C++, Verilog is case sensitive.
Identifiers : An identifier is usually a variable. You can use any letter, digit, the underscore, or $. Identifiers may not begin with a digit and may not be the same as a Verilog key word. As in C++ variable names should be chosen to assist in documentation.
Signal values : signals in Verilog have one of four values. These are 0 (logic 0), 1 (logic 1), ?, X, or x ( don~Rt care or unknown), and Z or z for high impedance tri-state.
Parameters : a parameter in Verilog can be any Verilog constant. Parameters are used to generalize a design. For example a 4-bit adder becomes more useful as a design if it is put together as an n-bit adder where n is a parameter specified by the user before compilation. Parameter declarations are done immediately after the module declaration. Here are some typical parameter examples:
EXAMPLE:
parameter n = 12;
parameter [3:0]p1 = 4'b1011;
parameter n = 12, m = 32;
Memory : Verilog allows for two dimensional arrays which typically get used for memory spaces. For example reg[7:0] m[63:0]; declares m to be a two-dimensional array consisting of 64 eight-bit words. You can access any word as m[2] for example but you do not get access to the bits in the word unless you copy the word to another 8-bit reg variable.
Strings : Strings are delimited by " ... ", and cannot be on multiple lines.
"hello world"; // legal string
Number : Numbers in verilog are in the following format.
The size is always specified as a decimal number. If no is specified then the default size is at least 32bits and may be larger depending on the machine. Valid base formats are 'b , 'B , 'h , 'H 'd , 'D , 'o , 'O for binary, hexadecimal, decimal, and octal. Numbers consist of strings of digits (0-9, A-F, a-f, x, X, z, Z). The X's mean unknown, and the Z's mean high impedance If no base format is specified the number is assumed to be a decimal number. Some examples of valid numbers are:
EXAMPLE: Unsized constant numbers
659 // is a decimal number
'h 837FF // is a hexadecimal number
'o7460 // is an octal number
4af // is illegal (hexadecimal format requires ~Rh)
EXAMPLE: Sized constant numbers
4'b1001 // is a 4-bit binary number
5'D 3 // is a 5-bit decimal number
3'b01x // is a 3-bit number with the least
// significant bit unknown
12'hx // is a 12-bit unknown number
16'hz // is a 16-bit high-impedance number
EXAMPLE: Using sign with constant numbers
8'd -6 // this is illegal syntax
-8'd 6 // this defines the two~Rs complement of 6,
// held in 8 bits~Wequivalent to -(8~Rd 6)
4'hf // this denotes the 4-bit number ~Q1111~R, to
// be interpreted as a 2~Rs complement number,
// or ~Q-1~R. This is equivalent to -4~Rh 1
-4'sd15 // this is equivalent to -(-4~Rd 1), or ~Q0001~R.
EXAMPLE: Automatic left padding
reg [11:0] a, b, c, d;
initial begin
a = 'h x; // yields xxx
b = 'h 3x; // yields 03x
c = 'h z3; // yields zz3
d = 'h 0z3; // yields 0z3
end
reg [84:0] e, f, g;
e = 'h5; // yields {82{1'b0},3'b101}
f = 'hx; // yields {85{1'hx}}
g = 'hz; // yields {85{1'hz}}
EXAMPLE: Using underscore character in numbers
27_195_000
16'b0011_0101_0001_1111
32'h 12ab_f001
EXAMPLE: Real constants
1.2
0.1
2394.26331
1.2E12 (the exponent symbol can be e or E)
1.30e-2
0.1e-0
23E10
29E-2
236.123_763_e-12 (underscores are ignored)
Comments : Verilog comments are the same as in C++. Use // for a single line comment or /* */ for a multiline comment.
Punctuation : white spaces are ignored in Verilog. A semicolon is used to indicate the end of a command line and commas are typically used to separate elements in a list. Like C++, Verilog is case sensitive.
Identifiers : An identifier is usually a variable. You can use any letter, digit, the underscore, or $. Identifiers may not begin with a digit and may not be the same as a Verilog key word. As in C++ variable names should be chosen to assist in documentation.
Signal values : signals in Verilog have one of four values. These are 0 (logic 0), 1 (logic 1), ?, X, or x ( don~Rt care or unknown), and Z or z for high impedance tri-state.
Parameters : a parameter in Verilog can be any Verilog constant. Parameters are used to generalize a design. For example a 4-bit adder becomes more useful as a design if it is put together as an n-bit adder where n is a parameter specified by the user before compilation. Parameter declarations are done immediately after the module declaration. Here are some typical parameter examples:
EXAMPLE:
parameter n = 12;
parameter [3:0]p1 = 4'b1011;
parameter n = 12, m = 32;
Memory : Verilog allows for two dimensional arrays which typically get used for memory spaces. For example reg[7:0] m[63:0]; declares m to be a two-dimensional array consisting of 64 eight-bit words. You can access any word as m[2] for example but you do not get access to the bits in the word unless you copy the word to another 8-bit reg variable.
Strings : Strings are delimited by " ... ", and cannot be on multiple lines.
"hello world"; // legal string
Number : Numbers in verilog are in the following format.
The size is always specified as a decimal number. If no is specified then the default size is at least 32bits and may be larger depending on the machine. Valid base formats are 'b , 'B , 'h , 'H 'd , 'D , 'o , 'O for binary, hexadecimal, decimal, and octal. Numbers consist of strings of digits (0-9, A-F, a-f, x, X, z, Z). The X's mean unknown, and the Z's mean high impedance If no base format is specified the number is assumed to be a decimal number. Some examples of valid numbers are:
EXAMPLE: Unsized constant numbers
659 // is a decimal number
'h 837FF // is a hexadecimal number
'o7460 // is an octal number
4af // is illegal (hexadecimal format requires ~Rh)
EXAMPLE: Sized constant numbers
4'b1001 // is a 4-bit binary number
5'D 3 // is a 5-bit decimal number
3'b01x // is a 3-bit number with the least
// significant bit unknown
12'hx // is a 12-bit unknown number
16'hz // is a 16-bit high-impedance number
EXAMPLE: Using sign with constant numbers
8'd -6 // this is illegal syntax
-8'd 6 // this defines the two~Rs complement of 6,
// held in 8 bits~Wequivalent to -(8~Rd 6)
4'hf // this denotes the 4-bit number ~Q1111~R, to
// be interpreted as a 2~Rs complement number,
// or ~Q-1~R. This is equivalent to -4~Rh 1
-4'sd15 // this is equivalent to -(-4~Rd 1), or ~Q0001~R.
EXAMPLE: Automatic left padding
reg [11:0] a, b, c, d;
initial begin
a = 'h x; // yields xxx
b = 'h 3x; // yields 03x
c = 'h z3; // yields zz3
d = 'h 0z3; // yields 0z3
end
reg [84:0] e, f, g;
e = 'h5; // yields {82{1'b0},3'b101}
f = 'hx; // yields {85{1'hx}}
g = 'hz; // yields {85{1'hz}}
EXAMPLE: Using underscore character in numbers
27_195_000
16'b0011_0101_0001_1111
32'h 12ab_f001
EXAMPLE: Real constants
1.2
0.1
2394.26331
1.2E12 (the exponent symbol can be e or E)
1.30e-2
0.1e-0
23E10
29E-2
236.123_763_e-12 (underscores are ignored)
Index
Introduction
Syntax
Data Types
Operators
Assignments
Control Constructs
Procedural Timing Controls
Structure
Block Statements
Structured Procedures
Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!
Introduction
Syntax
Data Types
Operators
Assignments
Control Constructs
Procedural Timing Controls
Structure
Block Statements
Structured Procedures
Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!