|HOME |ABOUT |ARTICLES |ACK |FEEDBACK |TOC |LINKS |BLOG |JOBS |


Tutorials



UVM SEQUENCE 6



Exclusive Access



A sequence may need exclusive access to the driver which sequencer is arbitrating among multiple sequence. Some operations require that a series of transaction needs to be driven without any other transaction in between them. Then a exclusive access to the driver will allow to a sequence to complete its operation with out any other sequence operations in between them.

There are 2 mechanisms to get exclusive access:
Lock-unlcok
Grab-ungrab



Lock-Unlock


task lock(uvm_sequencer_base sequencer = Null)
function void unlock(uvm_sequencer_base sequencer = Null)



Using lock() method , a sequence can requests for exclusive access. A lock request will be arbitrated the same as any other request. A lock is granted after all earlier requests are completed and no other locks or grabs are blocking this sequence. A lock() is blocking task and when access is granted, it will unblock.

Using unlock(), removes any locks or grabs obtained by this sequence on the specified sequencer.

If sequencer is null, the lock/unlock will be applied on the current default sequencer.

Lets see an example,
In this example there are 3 sequences with each sequence generating 4 transactions. All these 3 sequences will be called in parallel in another sequence.


(S)Sequence 1 code:

virtual task body();
repeat(4) begin
`uvm_do_with(req, { inst == PUSH_A; });
end
endtask

(S)Sequence 2 code:
virtual task body();
repeat(4) begin
`uvm_do_with(req, { inst == POP_C; });
end
endtask



(S)Sequence 3 code:


In this sequence , call the lock() method to get the exclusive access to driver.
After completing all the transaction driving, then call the unclock() method.


virtual task body();
lock();
repeat(4) begin
`uvm_do_with(req, { inst == PUSH_B; });
end
unlock();
endtask


(S)Parallel sequence code:

virtual task body();
fork
`uvm_do(s_a)
`uvm_do(s_b)
`uvm_do(s_c)
join
endtask

(S)Download the example


uvm_sequence_11.tar
Browse the code in uvm_sequence_11.tar


(S)Command to sun the simulation


VCS Users : make vcs
Questa Users: make questa



(S)Log file:

0: Driving Instruction PUSH_A
10: Driving Instruction POP_C
20: Driving Instruction PUSH_A
30: Driving Instruction PUSH_B
40: Driving Instruction PUSH_B
50: Driving Instruction PUSH_B
60: Driving Instruction PUSH_B
70: Driving Instruction POP_C
80: Driving Instruction PUSH_A
90: Driving Instruction POP_C
100: Driving Instruction PUSH_A
110: Driving Instruction POP_C



From the above log file, we can observe that , when seq_b sequence got the access, then transactions from seq_a and seq_c are not generated.

Lock() will be arbitrated before giving the access. To get the exclusive access without arbitration, grab() method should be used.



Grab-Ungrab


task grab(uvm_sequencer_base sequencer = null)
function void ungrab(uvm_sequencer_base sequencer = null)


grab() method requests a lock on the specified sequencer. A grab() request is put in front of the arbitration queue. It will be arbitrated before any other requests. A grab() is granted when no other grabs or locks are blocking this sequence.

A grab() is blocking task and when access is granted, it will unblock.

Ungrab() method removes any locks or grabs obtained by this sequence on the specified sequencer.
If no argument is supplied, then current default sequencer is chosen.

Example:


virtual task body();
#25;
grab();
repeat(4) begin
`uvm_do_with(req, { inst == PUSH_B; });
end
ungrab();
endtask

(S)Download the example


uvm_sequence_12.tar
Browse the code in uvm_sequence_12.tar


(S)Command to sun the simulation


VCS Users : make vcs
Questa Users: make questa




0: Driving Instruction PUSH_A
10: Driving Instruction POP_C
20: Driving Instruction PUSH_A
30: Driving Instruction PUSH_B
40: Driving Instruction PUSH_B
50: Driving Instruction PUSH_B
60: Driving Instruction PUSH_B
70: Driving Instruction POP_C
80: Driving Instruction PUSH_A
90: Driving Instruction POP_C
100: Driving Instruction PUSH_A
110: Driving Instruction POP_C

Index
Introduction
Uvm Testbench
Uvm Reporting
Uvm Transaction
Uvm Configuration
Uvm Factory
Uvm Sequence 1
Uvm Sequence 2
Uvm Sequence 3
Uvm Sequence 4
Uvm Sequence 5
Uvm Sequence 6
Uvm Tlm 1
Uvm Tlm 2
Uvm Callback

Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!





<< PREVIOUS PAGE

TOP

NEXT PAGE >>

copyright 2007-2017 :: all rights reserved www.testbench.in::Disclaimer