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FUNCTIONAL VERIFICATION NEED
Why we need functional verification?
To build confidence and stay in business.
A primary purpose for functional verification is to detect failures so that bugs can be identified and corrected before it gets shipped to costumer. If RTL designer makes a mistake in designing or coding, this results as a bug in the Chip. If this bug is executed, in certain situations the system will produce wrong results, causing a failure. Not all mistakes will necessarily result in failures. The bug in the dead code will never result in failure. A single mistake may result in a wide range of failure symptoms. Not all bugs are caused by coding errors. There are possibilities that error may in the specification itself. Sometimes miscommunications between teams may lead to wrong design.
Example of coding error:
1 reg [1:0] state;
2
3 parameter zero=0, one=1, two=2, three=3;
4
5 always @(state)
6 begin
7 case (State)
8 zero:
9 out = 4'b0000;
10 one:
11 out = 4'b0001;
12 two:
13 out = 4'b0010;
14 three:
15 out = 4'b0100;
16 default:
17 out = 4'b0000;
18 endcase
19 end
There is a coding error in the preceding example. Designer declared "state" in the line-1. Later in the code it is reference in the line-5. In the line-7 also, the designer intention is to refer "state". But mistakenly he typed "State". Verilog is a case-sensitive language, and variable "State" and "state" are different and this will produce wrong results.
Why we need functional verification?
To build confidence and stay in business.
A primary purpose for functional verification is to detect failures so that bugs can be identified and corrected before it gets shipped to costumer. If RTL designer makes a mistake in designing or coding, this results as a bug in the Chip. If this bug is executed, in certain situations the system will produce wrong results, causing a failure. Not all mistakes will necessarily result in failures. The bug in the dead code will never result in failure. A single mistake may result in a wide range of failure symptoms. Not all bugs are caused by coding errors. There are possibilities that error may in the specification itself. Sometimes miscommunications between teams may lead to wrong design.
Example of coding error:
1 reg [1:0] state;
2
3 parameter zero=0, one=1, two=2, three=3;
4
5 always @(state)
6 begin
7 case (State)
8 zero:
9 out = 4'b0000;
10 one:
11 out = 4'b0001;
12 two:
13 out = 4'b0010;
14 three:
15 out = 4'b0100;
16 default:
17 out = 4'b0000;
18 endcase
19 end
There is a coding error in the preceding example. Designer declared "state" in the line-1. Later in the code it is reference in the line-5. In the line-7 also, the designer intention is to refer "state". But mistakenly he typed "State". Verilog is a case-sensitive language, and variable "State" and "state" are different and this will produce wrong results.
Index
Asic Design
Bottle Neck In Asic Flow
Functional Verification Need
Testbench
Linear Testbench
Linear Random Testbench
How To Check The Results
Self Checking Testbenchs
How To Get Scenarios Which We Never Thought
How To Check Whether The Testbench Has Satisfactorily Exercised The Design
Types Of Code Coverage
Statement Coverage
Block Coverage
Conditional Coverage
Branch Coverage
Path Coverage
Toggle Coverage
Fsm Coverage
Make Your Goal 100 Percent Code Coverage Nothing Less
Functional Coverage
Coverage Driven Constraint Random Verification Architecture
Phases Of Verification
Ones Counter Example
Verification Plan
Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!
Asic Design
Bottle Neck In Asic Flow
Functional Verification Need
Testbench
Linear Testbench
Linear Random Testbench
How To Check The Results
Self Checking Testbenchs
How To Get Scenarios Which We Never Thought
How To Check Whether The Testbench Has Satisfactorily Exercised The Design
Types Of Code Coverage
Statement Coverage
Block Coverage
Conditional Coverage
Branch Coverage
Path Coverage
Toggle Coverage
Fsm Coverage
Make Your Goal 100 Percent Code Coverage Nothing Less
Functional Coverage
Coverage Driven Constraint Random Verification Architecture
Phases Of Verification
Ones Counter Example
Verification Plan
Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!