Random TestBench don't use Hardcoded values like linear testbenchs. Input stimulus is generated using random values. In Verilog, system function $random provides a mechanism for generating random numbers. The function returns a new 32-bit random number each time it is called. These test cases are not easily readable and are also not reusable. New tests have to be created when the specification or design changes, to accommodate the changes. The main disadvantage of this testing is that we never know what random values are generated and it may waste simulation cycles by generating same values again and again.
EXAMPLE: Linear Random TestBench module adder(a,b,c); //DUT code start
input [15:0] a,b;
output [16:0] c;
assign c = a + b;
endmodule //DUT code end