In this tutorial, we will verify the Switch RTL core using VMM in SystemVerilog. Following are the steps we follow to verify the Switch RTL core.

1) Understand the specification

2) Developing Verification Plan

3) Building the Verification Environment. We will build the Environment in Multiple phases, so it will be easy for you to lean step by step.

Phase 1) We will develop the testcase and interfaces, and integrate them in these with the DUT in top module.

Phase 2) We will Develop the Environment class.

Phase 3) We will develop reset and configuration methods in Environment class. Then using these methods, we will reset the DUT and configure the port address.

Phase 4) We will develop a packet class based on the stimulus plan. We will also write a small code to test the packet class implementation.

Phase 5) We will create atomic generator in the environment class.

Phase 6) We will develop a driver class. Packets are taken from the generator and sent to DUT using driver.

Phase 7) We will develop receiver class. Receiver collects the packets coming from the output port of the DUT.

Phase 8) We will develop scoreboard class which does the comparison of the expected packet with the actual packet received from the DUT.

Phase 9) We will develop coverage class based on the coverage plan. Coverage is sampled using the driver callbacks.

Verification Plan
Phase 1 Top
Phase 2 Environment
Phase 3 Reset
Phase 4 Packet
Phase 5 Generator
Phase 6 Driver
Phase 7 Receiver
Phase 8 Scoreboard
Phase 9 Coverage

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