|HOME |ABOUT |ARTICLES |ACK |FEEDBACK |TOC |LINKS |BLOG |JOBS |


Tutorials



PHASE 1 TOP




In phase 1,

1) We will write SystemVerilog Interfaces for input port, output port and memory port.
2) We will write Top module where testcase and DUT instances are done.
3) DUT and TestBench interfaces are connected in top module.
4) Clock is generator in top module.



NOTE: In every file you will see the syntax
`ifndef GUARD_*
`endif GUARD_*


Interfaces





In the interface.sv file, declare the 3 interfaces in the following way.
All the interfaces has clock as input.
All the signals in interface are wire type.
All the signals are synchronized to clock except reset in clocking block.

This approach will avoid race conditions between the design and the verification environment.
Define the set-up and hold time using parameters.
Signal directional w.r.t TestBench is specified with modport.





`ifndef GUARD_INTERFACE
`define GUARD_INTERFACE

//////////////////////////////////////////
// Interface declaration for the memory///
//////////////////////////////////////////

interface mem_interface(input bit clock);

parameter setup_time = 5ns;
parameter hold_time = 3ns;

wire [7:0] mem_data;
wire [1:0] mem_add;
wire mem_en;
wire mem_rd_wr;

clocking cb@(posedge clock);
default input #setup_time output #hold_time;
output mem_data;
output mem_add;
output mem_en;
output mem_rd_wr;
endclocking:cb

modport MEM(clocking cb,input clock);

endinterface :mem_interface

////////////////////////////////////////////
// Interface for the input side of switch.//
// Reset signal is also passed hear. //
////////////////////////////////////////////
interface input_interface(input bit clock);

parameter setup_time = 5ns;
parameter hold_time = 3ns;

wire data_status;
wire [7:0] data_in;
wire reset;

clocking cb@(posedge clock);
default input #setup_time output #hold_time;
output data_status;
output data_in;
endclocking:cb

modport IP(clocking cb,output reset,input clock);

endinterface:input_interface

/////////////////////////////////////////////////
// Interface for the output side of the switch.//
// output_interface is for only one output port//
/////////////////////////////////////////////////

interface output_interface(input bit clock);

parameter setup_time = 5ns;
parameter hold_time = 3ns;

wire [7:0] data_out;
wire ready;
wire read;

clocking cb@(posedge clock);
default input #setup_time output #hold_time;
input data_out;
input ready;
output read;
endclocking:cb

modport OP(clocking cb,input clock);

endinterface:output_interface


//////////////////////////////////////////////////

`endif


Testcase



Testcase is a program block which provides an entry point for the test and creates a scope that encapsulates program-wide data. Currently this is an empty testcase which just ends the simulation. Program block contains all the above declared interfaces as arguments. This testcase has initial and final blocks.

Inside the program block, include the vmm.sv file.



`ifndef GUARD_TESTCASE
`define GUARD_TESTCASE

program testcase(mem_interface.MEM mem_intf,input_interface.IP input_intf,output_interface.OP output_intf[4]);

`include "vmm.sv"

initial
begin
$display(" ******************* Start of testcase ****************");

#1000;
end

final
$display(" ******************** End of testcase *****************");

endprogram
`endif

Top Module



The modules that are included in the source text but are not instantiated are called top modules. This module is the highest scope of modules. Generally this module is named as "top" and referenced as "top module". Module name can be anything.
This top-level module will contain the design portion of the simulation.

Do the following in the top module:


1)Generate the clock signal.


bit Clock;

initial
begin
#20;
forever #10 Clock = ~Clock;
end



2)Do the instances of memory interface.



mem_interface mem_intf(Clock);



3)Do the instances of input interface.



input_interface input_intf(Clock);



4)There are 4 output ports. So do 4 instances of output_interface.



output_interface output_intf[4](Clock);



5)Do the instance of testcase and pass all the above declared interfaces.



testcase TC (mem_intf,input_intf,output_intf);



6)Do the instance of DUT.



switch DUT (.



7)Connect all the interfaces and DUT. The design which we have taken is in verilog. So Verilog DUT instance is connected signal by signal.



switch DUT (.clk(Clock),
.reset(input_intf.reset),
.data_status(input_intf.data_status),
.data(input_intf.data_in),
.port0(output_intf[0].data_out),
.port1(output_intf[1].data_out),
.port2(output_intf[2].data_out),
.port3(output_intf[3].data_out),
.ready_0(output_intf[0].ready),
.ready_1(output_intf[1].ready),
.ready_2(output_intf[2].ready),
.ready_3(output_intf[3].ready),
.read_0(output_intf[0].read),
.read_1(output_intf[1].read),
.read_2(output_intf[2].read),
.read_3(output_intf[3].read),
.mem_en(mem_intf.mem_en),
.mem_rd_wr(mem_intf.mem_rd_wr),
.mem_add(mem_intf.mem_add),
.mem_data(mem_intf.mem_data));








Top Module Source Code:


`ifndef GUARD_TOP
`define GUARD_TOP

module top();

/////////////////////////////////////////////////////
// Clock Declaration and Generation //
/////////////////////////////////////////////////////
bit Clock;

initial
begin
#20;
forever #10 Clock = ~Clock;
end
/////////////////////////////////////////////////////
// Memory interface instance //
/////////////////////////////////////////////////////

mem_interface mem_intf(Clock);

/////////////////////////////////////////////////////
// Input interface instance //
/////////////////////////////////////////////////////

input_interface input_intf(Clock);

/////////////////////////////////////////////////////
// output interface instance //
/////////////////////////////////////////////////////

output_interface output_intf[4](Clock);

/////////////////////////////////////////////////////
// Program block Testcase instance //
/////////////////////////////////////////////////////

testcase TC (mem_intf,input_intf,output_intf);

/////////////////////////////////////////////////////
// DUT instance and signal connection //
/////////////////////////////////////////////////////

switch DUT (.clk(Clock),
.reset(input_intf.reset),
.data_status(input_intf.data_status),
.data(input_intf.data_in),
.port0(output_intf[0].data_out),
.port1(output_intf[1].data_out),
.port2(output_intf[2].data_out),
.port3(output_intf[3].data_out),
.ready_0(output_intf[0].ready),
.ready_1(output_intf[1].ready),
.ready_2(output_intf[2].ready),
.ready_3(output_intf[3].ready),
.read_0(output_intf[0].read),
.read_1(output_intf[1].read),
.read_2(output_intf[2].read),
.read_3(output_intf[3].read),
.mem_en(mem_intf.mem_en),
.mem_rd_wr(mem_intf.mem_rd_wr),
.mem_add(mem_intf.mem_add),
.mem_data(mem_intf.mem_data));


endmodule


`endif


(S)Download the phase 1 files:


vmm_switch_1.tar
Browse the code in vmm_switch_1.tar


(S)Run the simulation:
vcs -sverilog -f filelist -R -ntb_opts rvm

(S)Log file after simulation:

******************* Start of testcase ****************
******************** End of testcase *****************

Index
Introduction
Specification
Verification Plan
Phase 1 Top
Phase 2 Environment
Phase 3 Reset
Phase 4 Packet
Phase 5 Generator
Phase 6 Driver
Phase 7 Receiver
Phase 8 Scoreboard
Phase 9 Coverage

Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!





<< PREVIOUS PAGE

TOP

NEXT PAGE >>

copyright 2007-2017 :: all rights reserved www.testbench.in::Disclaimer