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STATIC CONSTRAINT




If a constraint block is declared as static, then constraint mode on that block will effect on all the instancess of that class. In the following example, two objects obj_1 and obj_2 are declared. Constraints Var1_c is static and Var2_c is not static. When constraint_mode is used to switch off the constraints in in obj_2, constraint var1_c in obj_1 is also switched off.



EXAMPLE:
class A;
rand integer Var1, Var2;
static constraint Var1_c { Var1 == 10 ;}
constraint Var2_c { Var2 == 10 ;}
endclass

program A_p_46;
A obj_1 = new;
A obj_2 = new;
initial
begin
obj_2.Var1_c.constraint_mode(0);
obj_2.Var2_c.constraint_mode(0);
repeat(10)
begin
void'(obj_1.randomize());
$display("obj_1.Var1 : %d ,obj_1.Var2 : %d ",obj_1.Var1,obj_1.Var2);
end
end
endprogram

RESULTS:

# obj_1.Var1 : 733126180 ,obj_1.Var2 : 10
# obj_1.Var1 : -119008195 ,obj_1.Var2 : 10
# obj_1.Var1 : 342785185 ,obj_1.Var2 : 10
# obj_1.Var1 : 679818185 ,obj_1.Var2 : 10
# obj_1.Var1 : -717162992 ,obj_1.Var2 : 10
# obj_1.Var1 : 664520634 ,obj_1.Var2 : 10
# obj_1.Var1 : -1944980214 ,obj_1.Var2 : 10
# obj_1.Var1 : -1350759145 ,obj_1.Var2 : 10
# obj_1.Var1 : -1374963034 ,obj_1.Var2 : 10
# obj_1.Var1 : -462078992 ,obj_1.Var2 : 10

Index
Constrained Random Verification
Verilog Crv
Systemverilog Crv
Randomizing Objects
Random Variables
Randomization Methods
Checker
Constraint Block
Inline Constraint
Global Constraint
Constraint Mode
External Constraints
Randomization Controlability
Static Constraint
Constraint Expression
Variable Ordering
Constraint Solver Speed
Randcase
Randsequence
Random Stability
Array Randomization
Constraint Guards
Titbits

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