Historically,verification engineers used directed test bench to verify the functionality of their design.Rapid changes have occurred during the past decades in design and verification.High Level Verification Languages (HVLS) such as e, System c,Vera,SystemVerilog have become a necessity for verification environments.
Constraint Random stimulus generation is not new. Everybody uses verilog and VHDL at very low level abstraction for this purpose. HVLS provide constructs to express specification of stimulus at high level of abstraction and constraint solver generates legal stimulus.
Writing constraints at higher level of absctraction,makes the programming closer to spec.
A constraint language should support:
Expressions to complex scenarios.
Felxibility to control dynamically.
Combinational and sequential constraints.
Combinational constraint :
In ethernet, 13 & 14 th bytes should be equal to payload length.
If request comes, then acknoldegement should be given between 4th to 10th cycles.
NOTE:SystemVerilog doec not support sequential constraints.
This article is about Constrained random verification using SystemVerilog.I tried to explain every point using examples.